- let
- -- Lookup the scrutinee (which must be a variable bound to a tuple) in
- -- the existing bindings list and get the portname map for each of
- -- it's elements.
- Tuple tuple_ports = Maybe.fromMaybe
- (error $ "Case expression uses unknown scrutinee " ++ getOccString v)
- (lookup v binds)
- -- TODO include b in the binds list
- -- Merge our existing binds with the new binds.
- binds' = (zip bind_vars tuple_ports) ++ binds
- in
- -- Expand the expression with the new binds list
- expandExpr binds' expr
-
-expandSingleAltCaseExpr _ _ _ alt =
- error $ "Case patterns other than data constructors not supported in case alternative: " ++ (showSDoc $ ppr alt)
-
-
--- Expands the application of argument to a function into VHDL
-expandApplicationExpr ::
- [(CoreBndr, SignalNameMap)]
- -- A list of bindings in effect
- -> Type -- The result type of the function call
- -> Var.Var -- The function to call
- -> [CoreExpr] -- A list of argumetns to apply to the function
- -> VHDLState ( [AST.SigDec], [AST.ConcSm], [SignalNameMap], SignalNameMap)
- -- See expandExpr
-expandApplicationExpr binds ty f args = do
- let name = getOccString f
- -- Generate a unique name for the application
- appname <- uniqueName ("app_" ++ name)
- -- Lookup the hwfunction to instantiate
- HWFunction vhdl_id inports outport <- getHWFunc (appToHsFunction f args ty)
- -- Expand each of the args, so each of them is reduced to output signals
- (arg_signal_decls, arg_statements, arg_res_signals) <- expandArgs binds args
- -- Bind each of the input ports to the expanded arguments
- let inmaps = concat $ zipWith createAssocElems inports arg_res_signals
- -- Create signal names for our result
- let res_signal = getPortNameMapForTy (appname ++ "_out") ty
- -- Create the corresponding signal declarations
- let signal_decls = mkSignalsFromMap res_signal
- -- Bind each of the output ports to our output signals
- let outmaps = mapOutputPorts outport res_signal
- -- Instantiate the component
- let component = AST.CSISm $ AST.CompInsSm
- (AST.unsafeVHDLBasicId appname)
- (AST.IUEntity (AST.NSimple vhdl_id))
- (AST.PMapAspect (inmaps ++ outmaps))
- -- Merge the generated declarations
- return (
- signal_decls ++ arg_signal_decls,
- component : arg_statements,
- [], -- We don't take any extra arguments; we don't support higher order functions yet
- res_signal)
-
--- Creates a list of AssocElems (port map lines) that maps the given signals
--- to the given ports.
-createAssocElems ::
- SignalNameMap -- The port names to bind to
- -> SignalNameMap -- The signals to bind to it
- -> [AST.AssocElem] -- The resulting port map lines
-
-createAssocElems (Single (port_id, _)) (Single (signal_id, _)) =
- [(Just port_id) AST.:=>: (AST.ADName (AST.NSimple signal_id))]
-
-createAssocElems (Tuple ports) (Tuple signals) =
- concat $ zipWith createAssocElems ports signals
-
--- Generate a signal declaration for a signal with the given name and the
--- given type and no value. Also returns the id of the signal.
-mkSignal :: String -> AST.TypeMark -> (AST.VHDLId, AST.SigDec)
-mkSignal name ty =
- (id, mkSignalFromId id ty)
- where
- id = AST.unsafeVHDLBasicId name
-
-mkSignalFromId :: AST.VHDLId -> AST.TypeMark -> AST.SigDec
-mkSignalFromId id ty =
- AST.SigDec id ty Nothing
-
--- Generates signal declarations for all the signals in the given map
-mkSignalsFromMap ::
- SignalNameMap
- -> [AST.SigDec]
-
-mkSignalsFromMap (Single (id, ty)) =
- [mkSignalFromId id ty]
-
-mkSignalsFromMap (Tuple signals) =
- concat $ map mkSignalsFromMap signals
-
-expandArgs ::
- [(CoreBndr, SignalNameMap)] -- A list of bindings in effect
- -> [CoreExpr] -- The arguments to expand
- -> VHDLState ([AST.SigDec], [AST.ConcSm], [SignalNameMap])
- -- The resulting signal declarations,
- -- component instantiations and a
- -- VHDLName for each of the
- -- expressions passed in.
-expandArgs binds (e:exprs) = do
- -- Expand the first expression
- (signal_decls, statements, arg_signals, res_signal) <- expandExpr binds e
- if not (null arg_signals)
- then error $ "Passing functions as arguments not supported: " ++ (showSDoc $ ppr e)
- else do
- (signal_decls', statements', res_signals') <- expandArgs binds exprs
- return (
- signal_decls ++ signal_decls',
- statements ++ statements',
- res_signal : res_signals')
-
-expandArgs _ [] = return ([], [], [])
-
--- Extract the arguments from a data constructor application (that is, the
--- normal args, leaving out the type args).
-dataConAppArgs :: DataCon -> [CoreExpr] -> [CoreExpr]
-dataConAppArgs dc args =
- drop tycount args
- where
- tycount = length $ DataCon.dataConAllTyVars dc
-
-mapOutputPorts ::
- SignalNameMap -- The output portnames of the component
- -> SignalNameMap -- The output portnames and/or signals to map these to
- -> [AST.AssocElem] -- The resulting output ports
-
--- Map the output port of a component to the output port of the containing
--- entity.
-mapOutputPorts (Single (portname, _)) (Single (signalname, _)) =
- [(Just portname) AST.:=>: (AST.ADName (AST.NSimple signalname))]
-
--- Map matching output ports in the tuple
-mapOutputPorts (Tuple ports) (Tuple signals) =
- concat (zipWith mapOutputPorts ports signals)
-
-expandBind ::
- CoreBind -- The binder to expand into VHDL
- -> VHDLState [AST.LibraryUnit] -- The resulting VHDL
-
-expandBind (Rec _) = error "Recursive binders not supported"
-
-expandBind bind@(NonRec var expr) = do
- -- Create the function signature
- (hsfunc, hwfunc) <- mkHWFunction bind
- -- Add it to the session
- addFunc hsfunc hwfunc
- arch <- getArchitecture hwfunc expr
- let entity = getEntity hwfunc
- return $ [
- AST.LUEntity entity,
- AST.LUArch arch ]
-
-getArchitecture ::
- HWFunction -- The function to generate an architecture for
- -> CoreExpr -- The expression that is bound to the function
- -> VHDLState AST.ArchBody -- The resulting architecture
-
-getArchitecture hwfunc expr = do
- -- Unpack our hwfunc
- let HWFunction vhdl_id inports outport = hwfunc
- -- Expand the expression into an architecture body
- (signal_decls, statements, arg_signals, res_signal) <- expandExpr [] expr
- let inport_assigns = concat $ zipWith createSignalAssignments arg_signals inports
- let outport_assigns = createSignalAssignments outport res_signal
- return $ AST.ArchBody
- (AST.unsafeVHDLBasicId "structural")
- (AST.NSimple vhdl_id)
- (map AST.BDISD signal_decls)
- (inport_assigns ++ outport_assigns ++ statements)
-
--- Generate a VHDL entity declaration for the given function
-getEntity :: HWFunction -> AST.EntityDec
-getEntity (HWFunction vhdl_id inports outport) =
- AST.EntityDec vhdl_id ports
- where
- ports =
- (concat $ map (mkIfaceSigDecs AST.In) inports)
- ++ mkIfaceSigDecs AST.Out outport
-
-mkIfaceSigDecs ::
- AST.Mode -- The port's mode (In or Out)
- -> SignalNameMap -- The ports to generate a map for
- -> [AST.IfaceSigDec] -- The resulting ports
-
-mkIfaceSigDecs mode (Single (port_id, ty)) =
- [AST.IfaceSigDec port_id mode ty]
-
-mkIfaceSigDecs mode (Tuple ports) =
- concat $ map (mkIfaceSigDecs mode) ports
-
--- Create concurrent assignments of one map of signals to another. The maps
--- should have a similar form.
-createSignalAssignments ::
- SignalNameMap -- The signals to assign to
- -> SignalNameMap -- The signals to assign
- -> [AST.ConcSm] -- The resulting assignments
-
--- A simple assignment of one signal to another (greatly complicated because
--- signal assignments can be conditional with multiple conditions in VHDL).
-createSignalAssignments (Single (dst, _)) (Single (src, _)) =
- [AST.CSSASm assign]
- where
- src_name = AST.NSimple src
- src_expr = AST.PrimName src_name
- src_wform = AST.Wform [AST.WformElem src_expr Nothing]
- dst_name = (AST.NSimple dst)
- assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
-
-createSignalAssignments (Tuple dsts) (Tuple srcs) =
- concat $ zipWith createSignalAssignments dsts srcs
-
-createSignalAssignments dst src =
- error $ "Non matching source and destination: " ++ show dst ++ "\nand\n" ++ show src
-
-type SignalNameMap = HsValueMap (AST.VHDLId, AST.TypeMark)
-
--- | A datatype that maps each of the single values in a haskell structure to
--- a mapto. The map has the same structure as the haskell type mapped, ie
--- nested tuples etc.
-data HsValueMap mapto =
- Tuple [HsValueMap mapto]
- | Single mapto
- deriving (Show, Eq)
-
--- | Creates a HsValueMap with the same structure as the given type, using the
--- given function for mapping the single types.
-mkHsValueMap ::
- (Type -> HsValueMap mapto) -- ^ A function to map single value Types
- -- (basically anything but tuples) to a
- -- HsValueMap (not limited to the Single
- -- constructor)
- -> Type -- ^ The type to map to a HsValueMap
- -> HsValueMap mapto -- ^ The resulting map
-
-mkHsValueMap f ty =
- case Type.splitTyConApp_maybe ty of
- Just (tycon, args) ->
- if (TyCon.isTupleTyCon tycon)
- then
- -- Handle tuple construction especially
- Tuple (map (mkHsValueMap f) args)
- else
- -- And let f handle the rest
- f ty
- -- And let f handle the rest
- Nothing -> f ty
-
--- Generate a port name map (or multiple for tuple types) in the given direction for
--- each type given.
-getPortNameMapForTys :: String -> Int -> [Type] -> [SignalNameMap]
-getPortNameMapForTys prefix num [] = []
-getPortNameMapForTys prefix num (t:ts) =
- (getPortNameMapForTy (prefix ++ show num) t) : getPortNameMapForTys prefix (num + 1) ts
-
-getPortNameMapForTy :: String -> Type -> SignalNameMap
-getPortNameMapForTy name ty =
- if (TyCon.isTupleTyCon tycon) then
- -- Expand tuples we find
- Tuple (getPortNameMapForTys name 0 args)
- else -- Assume it's a type constructor application, ie simple data type
- Single ((AST.unsafeVHDLBasicId name), (vhdl_ty ty))