- -- Turns the given bind into VHDL
- mkVHDL :: UniqSupply.UniqSupply -> [(CoreBndr, CoreExpr)] -> [Bool] -> TranslatorState [(AST.VHDLId, AST.DesignFile)]
- mkVHDL uniqSupply binds statefuls = do
- let binds'' = map (Arrow.second $ normalize uniqSupply) binds
- let binds' = trace ("Before:\n\n" ++ showSDoc ( ppr binds ) ++ "\n\nAfter:\n\n" ++ showSDoc ( ppr binds'')) binds''
- -- Add the builtin functions
- --mapM addBuiltIn builtin_funcs
- -- Create entities and architectures for them
- --Monad.zipWithM processBind statefuls binds
- --modA tsFlatFuncs (Map.map nameFlatFunction)
- --flatfuncs <- getA tsFlatFuncs
- return $ VHDL.createDesignFiles binds'