mapOutputPorts ::
SignalNameMap AST.VHDLId -- The output portnames of the component
-> SignalNameMap AST.VHDLId -- The output portnames and/or signals to map these to
mapOutputPorts ::
SignalNameMap AST.VHDLId -- The output portnames of the component
-> SignalNameMap AST.VHDLId -- The output portnames and/or signals to map these to