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Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project
[matthijs/master-project/cλash.git]
/
Translator.hs
diff --git
a/Translator.hs
b/Translator.hs
index 3f60330b37a68b8680cdedec20996f28134c5a42..0f60277671f99b646ec427deb8fd82ce92d53169 100644
(file)
--- a/
Translator.hs
+++ b/
Translator.hs
@@
-52,8
+52,8
@@
import FlattenTypes
import VHDLTypes
import qualified VHDL
import VHDLTypes
import qualified VHDL
-main = do
-
makeVHDL "Adders.hs" "highordtest
" True
+
--
main = do
+
-- makeVHDL "Alu.hs" "exec
" True
makeVHDL :: String -> String -> Bool -> IO ()
makeVHDL filename name stateful = do
makeVHDL :: String -> String -> Bool -> IO ()
makeVHDL filename name stateful = do
@@
-62,7
+62,7
@@
makeVHDL filename name stateful = do
-- Translate to VHDL
vhdl <- moduleToVHDL core [(name, stateful)]
-- Write VHDL to file
-- Translate to VHDL
vhdl <- moduleToVHDL core [(name, stateful)]
-- Write VHDL to file
- let dir = ".
./vhdl
/vhdl/" ++ name ++ "/"
+ let dir = "./vhdl/" ++ name ++ "/"
mapM (writeVHDL dir) vhdl
return ()
mapM (writeVHDL dir) vhdl
return ()