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Add empty let removal normalization pass.
[matthijs/master-project/cλash.git]
/
Sim.hs
diff --git
a/Sim.hs
b/Sim.hs
index c87f7605e727bed37e47898e9feb8346d36ea607..5a8fe2d56c9b3a808619bf04c86127d6b065f3c8 100644
(file)
--- a/
Sim.hs
+++ b/
Sim.hs
@@
-1,4
+1,4
@@
-module Sim (simulate, SCircuit,
simulateIO
) where
+module Sim (simulate, SCircuit,
Circuit, simulateIO, stateless
) where
import Data.Typeable
simulate f input s = do
import Data.Typeable
simulate f input s = do
@@
-13,6
+13,7
@@
simulate f input s = do
-- A circuit with input of type a, state of type s and output of type b
type SCircuit i s o = i -> s -> (s, o)
-- A circuit with input of type a, state of type s and output of type b
type SCircuit i s o = i -> s -> (s, o)
+type Circuit i o = i -> o
run :: SCircuit i s o -> [i] -> s -> [(i, o, s)]
run f (i:input) s =
run :: SCircuit i s o -> [i] -> s -> [(i, o, s)]
run f (i:input) s =
@@
-49,4
+50,10
@@
printOutput (i, o, s) = do
putStr "\nNew State: "
putStr $ show s
putStr "\n\n"
putStr "\nNew State: "
putStr $ show s
putStr "\n\n"
+
+-- Takes a stateless circuit and turns it into a stateful circuit (with an
+-- empty state) so it can be used in simulation
+stateless :: Circuit i o -> SCircuit i () o
+stateless f = \i s -> (s, f i)
+
-- vim: set ts=8 sw=2 sts=2 expandtab:
-- vim: set ts=8 sw=2 sts=2 expandtab: