+instance Pretty SignalInfo where
+ pPrint (SignalInfo name use ty hints) =
+ text ":" <> (pPrint use) <> (ppname name)
+ where
+ ppname Nothing = empty
+ ppname (Just name) = text ":" <> text name
+
+instance Pretty SigUse where
+ pPrint SigPortIn = text "PI"
+ pPrint SigPortOut = text "PO"
+ pPrint SigInternal = text "I"
+ pPrint (SigStateOld n) = text "SO:" <> int n
+ pPrint (SigStateNew n) = text "SN:" <> int n
+ pPrint SigSubState = text "s"
+
+instance Pretty TranslatorSession where
+ pPrint (TranslatorSession mod nameCount flatfuncs) =
+ text "Module: " $$ nest 15 (text modname)
+ $+$ text "NameCount: " $$ nest 15 (int nameCount)
+ $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList flatfuncs)))
+ where
+ ppfunc (hsfunc, flatfunc) =
+ pPrint hsfunc $+$ nest 5 (pPrint flatfunc)
+ modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
+{-
+instance Pretty FuncData where
+ pPrint (FuncData flatfunc entity arch) =
+ text "Flattened: " $$ nest 15 (ppffunc flatfunc)
+ $+$ text "Entity" $$ nest 15 (ppent entity)
+ $+$ pparch arch
+ where
+ ppffunc (Just f) = pPrint f
+ ppffunc Nothing = text "Nothing"
+ ppent (Just e) = pPrint e
+ ppent Nothing = text "Nothing"
+ pparch Nothing = text "VHDL architecture not present"
+ pparch (Just _) = text "VHDL architecture present"
+-}