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Add an importModule function.
[matthijs/master-project/cλash.git]
/
Pretty.hs
diff --git
a/Pretty.hs
b/Pretty.hs
index edfe05b41be06c8c74519af88a8752b00f746dc9..ef92c4dc955aeffe47dfb0877ad1b08f80abbae3 100644
(file)
--- a/
Pretty.hs
+++ b/
Pretty.hs
@@
-97,15
+97,15
@@
instance Pretty SigUse where
pPrint SigSubState = text "s"
instance Pretty TranslatorSession where
pPrint SigSubState = text "s"
instance Pretty TranslatorSession where
- pPrint (
VHDLSession mod nameCount
funcs) =
+ pPrint (
TranslatorSession mod nameCount flat
funcs) =
text "Module: " $$ nest 15 (text modname)
$+$ text "NameCount: " $$ nest 15 (int nameCount)
text "Module: " $$ nest 15 (text modname)
$+$ text "NameCount: " $$ nest 15 (int nameCount)
- $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
+ $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList f
latf
uncs)))
where
where
- ppfunc (hsfunc, f
data
) =
- pPrint hsfunc $+$ nest 5 (pPrint f
data
)
+ ppfunc (hsfunc, f
latfunc
) =
+ pPrint hsfunc $+$ nest 5 (pPrint f
latfunc
)
modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
-
+{-
instance Pretty FuncData where
pPrint (FuncData flatfunc entity arch) =
text "Flattened: " $$ nest 15 (ppffunc flatfunc)
instance Pretty FuncData where
pPrint (FuncData flatfunc entity arch) =
text "Flattened: " $$ nest 15 (ppffunc flatfunc)
@@
-118,19
+118,13
@@
instance Pretty FuncData where
ppent Nothing = text "Nothing"
pparch Nothing = text "VHDL architecture not present"
pparch (Just _) = text "VHDL architecture present"
ppent Nothing = text "Nothing"
pparch Nothing = text "VHDL architecture not present"
pparch (Just _) = text "VHDL architecture present"
+-}
instance Pretty Entity where
instance Pretty Entity where
- pPrint (Entity id args res
decl pkg
) =
+ pPrint (Entity id args res) =
text "Entity: " $$ nest 10 (pPrint id)
$+$ text "Args: " $$ nest 10 (pPrint args)
$+$ text "Result: " $$ nest 10 (pPrint res)
text "Entity: " $$ nest 10 (pPrint id)
$+$ text "Args: " $$ nest 10 (pPrint args)
$+$ text "Result: " $$ nest 10 (pPrint res)
- $+$ ppdecl decl
- $+$ pppkg pkg
- where
- ppdecl Nothing = text "VHDL entity not present"
- ppdecl (Just _) = text "VHDL entity present"
- pppkg Nothing = text "VHDL package not present"
- pppkg (Just _) = text "VHDL package present"
instance (OutputableBndr b, Show b) => Pretty (CoreSyn.Bind b) where
pPrint (CoreSyn.NonRec b expr) =
instance (OutputableBndr b, Show b) => Pretty (CoreSyn.Bind b) where
pPrint (CoreSyn.NonRec b expr) =
@@
-147,3
+141,10
@@
prettyBind (b, expr) =
where
b' = show b
expr' = show expr
where
b' = show b
expr' = show expr
+
+instance (Pretty k, Pretty v) => Pretty (Map.Map k v) where
+ pPrint =
+ vcat . map ppentry . Map.toList
+ where
+ ppentry (k, v) =
+ pPrint k <> text " : " $$ nest 15 (pPrint v)