+ pPrint (CondDef _ _ _ _) = text "TODO"
+ pPrint (UncondDef src dst) = text "TODO"
+
+instance Pretty SignalInfo where
+ pPrint (SignalInfo name use ty) =
+ text ":" <> (pPrint use) <> (ppname name)
+ where
+ ppname Nothing = empty
+ ppname (Just name) = text ":" <> text name
+
+instance Pretty SigUse where
+ pPrint SigPortIn = text "PI"
+ pPrint SigPortOut = text "PO"
+ pPrint SigInternal = text "I"
+ pPrint (SigStateOld n) = text "SO:" <> int n
+ pPrint (SigStateNew n) = text "SN:" <> int n
+ pPrint SigSubState = text "s"
+
+instance Pretty VHDLSession where
+ pPrint (VHDLSession mod nameCount funcs) =
+ text "Module: " $$ nest 15 (text modname)
+ $+$ text "NameCount: " $$ nest 15 (int nameCount)
+ $+$ text "Functions: " $$ nest 15 (vcat (map ppfunc (Map.toList funcs)))
+ where
+ ppfunc (hsfunc, fdata) =
+ pPrint hsfunc $+$ nest 5 (pPrint fdata)
+ modname = showSDoc $ Module.pprModule (HscTypes.cm_module mod)
+
+instance Pretty FuncData where
+ pPrint (FuncData flatfunc entity arch) =
+ text "Flattened: " $$ nest 15 (ppffunc flatfunc)
+ $+$ text "Entity" $$ nest 15 (ppent entity)
+ $+$ pparch arch
+ where
+ ppffunc (Just f) = pPrint f
+ ppffunc Nothing = text "Nothing"
+ ppent (Just e) = pPrint e
+ ppent Nothing = text "Nothing"
+ pparch Nothing = text "VHDL architecture not present"
+ pparch (Just _) = text "VHDL architecture present"
+
+instance Pretty Entity where
+ pPrint (Entity id args res decl) =
+ text "Entity: " $$ nest 10 (pPrint id)
+ $+$ text "Args: " $$ nest 10 (pPrint args)
+ $+$ text "Result: " $$ nest 10 (pPrint res)
+ $+$ ppdecl decl
+ where
+ ppdecl Nothing = text "VHDL entity not present"
+ ppdecl (Just _) = text "VHDL entity present"
+
+instance (OutputableBndr b, Show b) => Pretty (CoreSyn.Bind b) where
+ pPrint (CoreSyn.NonRec b expr) =
+ text "NonRec: " $$ nest 10 (prettyBind (b, expr))
+ pPrint (CoreSyn.Rec binds) =
+ text "Rec: " $$ nest 10 (vcat $ map (prettyBind) binds)
+
+instance Pretty AST.VHDLId where
+ pPrint id = ForSyDe.Backend.Ppr.ppr id