-import Prelude hiding (
- null, length, head, tail, last, init, take, drop, (++), map, foldl, foldr,
- zipWith, zip, unzip, concat, reverse, iterate )
-import Bits
-import Types
-import Data.Param.TFVec
-import Data.RangedWord
-
-constant :: NaturalT n => e -> Op n e
-constant e a b =
- copy e
-
-invop :: Op n Bit
-invop a b = map hwnot a
-
-andop :: Op n Bit
-andop a b = zipWith hwand a b
-
--- Is any bit set?
---anyset :: (PositiveT n) => Op n Bit
-anyset :: NaturalT n => Op n Bit
---anyset a b = copy undefined (a' `hwor` b')
-anyset a b = constant (a' `hwor` b') a b
- where
- a' = foldl hwor Low a
- b' = foldl hwor Low b
-
-type Op n e = (TFVec n e -> TFVec n e -> TFVec n e)
-type Opcode = Bit
-
-alu :: Op n e -> Op n e -> Opcode -> TFVec n e -> TFVec n e -> TFVec n e
+import qualified Prelude as P
+import CLasH.HardwareTypes
+import CLasH.Translator.Annotations
+
+import HighOrdAluOps
+
+{-# ANN sim_input TestInput#-}
+sim_input :: [(Opcode, Vector D4 (SizedInt D8), Vector D4 (SizedInt D8))]
+sim_input = [ (High, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8])))
+ , (High, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8])))
+ , (Low, $(vectorTH ([4,3,2,1]::[SizedInt D8])), $(vectorTH ([1,2,3,4]::[SizedInt D8]))) ]
+
+{-# ANN actual_alu InitState #-}
+initstate = High
+
+alu :: Op n e -> Op n e -> Opcode -> Vector n e -> Vector n e -> Vector n e