- label = mkVHDLExtId ("mapVector" ++ (AST.fromVHDLId res))
- nPar = AST.unsafeVHDLBasicId "n"
- range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
- genScheme = AST.ForGn nPar range
- entity_id = ent_id entity
- argport = map (Monad.liftM fst) (ent_args entity)
- resport = (Monad.liftM fst) (ent_res entity)
- inport = mkAssocElemI (head argport) arg
- outport = mkAssocElemI resport res
- clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
- portmaps = Maybe.catMaybes [inport,outport,clk_port]
- portname = mkVHDLExtId ("map" ++ (AST.fromVHDLId entity_id))
- portmap = AST.CSISm $ AST.CompInsSm (AST.unsafeVHDLBasicId "map12") (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)
- genSm = AST.GenerateSm label genScheme [] [portmap]
- -- | Create an VHDL port -> signal association
- mkAssocElemI :: Maybe AST.VHDLId -> AST.VHDLId -> Maybe AST.AssocElem
- mkAssocElemI (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NIndexed (AST.IndexedName
- (AST.NSimple signal) [AST.PrimName $ AST.NSimple nPar])))
- mkAssocElemI Nothing _ = Nothing
- mkAssocElem :: Maybe AST.VHDLId -> String -> Maybe AST.AssocElem
- mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLExtId signal)))
- mkAssocElem Nothing _ = Nothing
- mkVHDLExtId :: String -> AST.VHDLId
- mkVHDLExtId s =
- AST.unsafeVHDLExtId $ strip_invalid s
- where
- -- Allowed characters, taken from ForSyde's mkVHDLExtId
- allowed = ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ " \"#&\\'()*+,./:;<=>_|!$%@?[]^`{}~-"
- strip_invalid = filter (`elem` allowed)
+ -- Setup the generate scheme
+ len = (tfvec_len . Var.varType) res
+ label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
+ nPar = AST.unsafeVHDLBasicId "n"
+ range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
+ genScheme = AST.ForGn nPar range
+ -- Get the entity name and port names
+ entity_id = ent_id entity
+ argports = map (Monad.liftM fst) (ent_args entity)
+ resport = (Monad.liftM fst) (ent_res entity)
+ -- Assign the ports
+ inport1 = mkAssocElemIndexed (argports!!0) (varToString arg1) nPar
+ inport2 = mkAssocElemIndexed (argports!!1) (varToString arg2) nPar
+ outport = mkAssocElemIndexed resport (varToString res) nPar
+ clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
+ portassigns = Maybe.catMaybes [inport1,inport2,outport,clk_port]
+ -- Generate the portmap
+ mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ genSm = AST.GenerateSm label genScheme [] [compins]