genMapCall entity [arg, res] = genSm
where
-- Setup the generate scheme
genMapCall entity [arg, res] = genSm
where
-- Setup the generate scheme
nPar = AST.unsafeVHDLBasicId "n"
range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
genScheme = AST.ForGn nPar range
nPar = AST.unsafeVHDLBasicId "n"
range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
genScheme = AST.ForGn nPar range
- inport = mkAssocElemIndexed (head argport) (bndrToString arg) nPar
- outport = mkAssocElemIndexed resport (bndrToString res) nPar
+ inport = mkAssocElemIndexed (head argport) (varToString arg) nPar
+ outport = mkAssocElemIndexed resport (varToString res) nPar
clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
portassigns = Maybe.catMaybes [inport,outport,clk_port]
-- Generate the portmap
mapLabel = "map" ++ (AST.fromVHDLId entity_id)
clk_port = mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
portassigns = Maybe.catMaybes [inport,outport,clk_port]
-- Generate the portmap
mapLabel = "map" ++ (AST.fromVHDLId entity_id)