+genFCall' (Right name) _ _ = error $ "Cannot generate builtin function call assigned to a VHDLName: " ++ show name
+
+-- | Generate a generate statement for the builtin function "map"
+genMap :: BuiltinBuilder
+genMap = genVarArgs genMap'
+genMap' (Left res) f [mapped_f, arg] = do
+ signatures <- getA vsSignatures
+ let entity = Maybe.fromMaybe
+ (error $ "Using function '" ++ (varToString mapped_f) ++ "' without signature? This should not happen!")
+ (Map.lookup mapped_f signatures)
+ let
+ -- Setup the generate scheme
+ len = (tfvec_len . Var.varType) res
+ -- TODO: Use something better than varToString
+ label = mkVHDLExtId ("mapVector" ++ (varToString res))
+ nPar = AST.unsafeVHDLBasicId "n"
+ range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
+ genScheme = AST.ForGn nPar range
+ -- Get the entity name and port names
+ entity_id = ent_id entity
+ argports = map (Monad.liftM fst) (ent_args entity)
+ resport = (Monad.liftM fst) (ent_res entity)
+ -- Assign the ports
+ inport = mkAssocElemIndexed (argports!!0) (varToVHDLId arg) nPar
+ outport = mkAssocElemIndexed resport (varToVHDLId res) nPar
+ portassigns = Maybe.catMaybes [inport,outport]
+ -- Generate the portmap
+ mapLabel = "map" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
+ in
+ return $ [genSm]
+genMap' (Right name) _ _ = error $ "Cannot generate map function call assigned to a VHDLName: " ++ show name
+
+genZipWith :: BuiltinBuilder
+genZipWith = genVarArgs genZipWith'
+genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
+genZipWith' (Left res) f args@[zipped_f, arg1, arg2] = do
+ signatures <- getA vsSignatures
+ let entity = Maybe.fromMaybe
+ (error $ "Using function '" ++ (varToString zipped_f) ++ "' without signature? This should not happen!")
+ (Map.lookup zipped_f signatures)
+ let
+ -- Setup the generate scheme
+ len = (tfvec_len . Var.varType) res
+ -- TODO: Use something better than varToString
+ label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
+ nPar = AST.unsafeVHDLBasicId "n"
+ range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
+ genScheme = AST.ForGn nPar range
+ -- Get the entity name and port names
+ entity_id = ent_id entity
+ argports = map (Monad.liftM fst) (ent_args entity)
+ resport = (Monad.liftM fst) (ent_res entity)
+ -- Assign the ports
+ inport1 = mkAssocElemIndexed (argports!!0) (varToVHDLId arg1) nPar
+ inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId arg2) nPar
+ outport = mkAssocElemIndexed resport (varToVHDLId res) nPar
+ portassigns = Maybe.catMaybes [inport1,inport2,outport]
+ -- Generate the portmap
+ mapLabel = "zipWith" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ genSm = AST.CSGSm $ AST.GenerateSm label genScheme [] [compins]
+ in
+ return $ [genSm]
+{-
+genFoldl :: BuiltinBuilder
+genFoldl = genVarArgs genFoldl'
+genFoldl' resVal f [folded_f, startVal, inVec] = do
+ signatures <- getA vsSignatures
+ let entity = Maybe.fromMaybe
+ (error $ "Using function '" ++ (varToString folded_f) ++ "' without signature? This should not happen!")
+ (Map.lookup folded_f signatures)
+ let (vec, _) = splitAppTy (Var.varType inVec)
+ let vecty = Type.mkAppTy vec (Var.varType startVal)
+ vecType <- vhdl_ty vecty
+ -- Setup the generate scheme
+ let len = (tfvec_len . Var.varType) inVec
+ let genlabel = mkVHDLExtId ("foldlVector" ++ (varToString inVec))
+ let blockLabel = mkVHDLExtId ("foldlVector" ++ (varToString startVal))
+ let range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
+ let genScheme = AST.ForGn (AST.unsafeVHDLBasicId "n") range
+ -- Make the intermediate vector
+ let tmpVec = AST.BDISD $ AST.SigDec (mkVHDLExtId "tmp") vecType Nothing
+ -- Get the entity name and port names
+ let entity_id = ent_id entity
+ let argports = map (Monad.liftM fst) (ent_args entity)
+ let resport = (Monad.liftM fst) (ent_res entity)
+ -- Return the generate functions
+ let genSm = AST.GenerateSm genlabel genScheme []
+ [ AST.CSGSm (genFirstCell (entity_id, argports, resport)
+ [startVal, inVec, resVal])
+ , AST.CSGSm (genOtherCell (entity_id, argports, resport)
+ [startVal, inVec, resVal])
+ , AST.CSGSm (genLastCell (entity_id, argports, resport)
+ [startVal, inVec, resVal])
+ ]
+ return $ [AST.CSBSm $ AST.BlockSm blockLabel [] (AST.PMapAspect []) [tmpVec] [AST.CSGSm genSm]]
+ where
+ genFirstCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
+ where
+ cellLabel = mkVHDLExtId "firstcell"
+ cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit "0"))
+ tmpId = mkVHDLExtId "tmp"
+ nPar = AST.unsafeVHDLBasicId "n"
+ -- Assign the ports
+ inport1 = mkAssocElem (argports!!0) (varToString startVal)
+ inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
+ outport = mkAssocElemIndexed resport tmpId nPar
+ portassigns = Maybe.catMaybes [inport1,inport2,outport]
+ -- Generate the portmap
+ mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
+ genOtherCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
+ where
+ len = (tfvec_len . Var.varType) inVec
+ cellLabel = mkVHDLExtId "othercell"
+ cellGenScheme = AST.IfGn $ AST.And ((AST.PrimName $ AST.NSimple nPar) AST.:>: (AST.PrimLit "0"))
+ ((AST.PrimName $ AST.NSimple nPar) AST.:<: (AST.PrimLit $ show (len-1)))
+ tmpId = mkVHDLExtId "tmp"
+ nPar = AST.unsafeVHDLBasicId "n"
+ -- Assign the ports
+ inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1")
+ inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
+ outport = mkAssocElemIndexed resport tmpId nPar
+ portassigns = Maybe.catMaybes [inport1,inport2,outport]
+ -- Generate the portmap
+ mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Return the generate functions
+ cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins]
+ genLastCell (entity_id, argports, resport) [startVal, inVec, resVal] = cellGn
+ where
+ len = (tfvec_len . Var.varType) inVec
+ cellLabel = mkVHDLExtId "lastCell"
+ cellGenScheme = AST.IfGn ((AST.PrimName $ AST.NSimple nPar) AST.:=: (AST.PrimLit $ show (len-1)))
+ tmpId = mkVHDLExtId "tmp"
+ nPar = AST.unsafeVHDLBasicId "n"
+ -- Assign the ports
+ inport1 = mkAssocElemIndexed (argports!!0) tmpId (AST.unsafeVHDLBasicId "n-1")
+ inport2 = mkAssocElemIndexed (argports!!1) (varToVHDLId inVec) nPar
+ outport = mkAssocElemIndexed resport tmpId nPar
+ portassigns = Maybe.catMaybes [inport1,inport2,outport]
+ -- Generate the portmap
+ mapLabel = "cell" ++ (AST.fromVHDLId entity_id)
+ compins = mkComponentInst mapLabel entity_id portassigns
+ -- Generate the output assignment
+ assign = mkUncondAssign (Left resVal) (AST.PrimName (AST.NIndexed (AST.IndexedName
+ (AST.NSimple tmpId) [AST.PrimLit $ show (len-1)])))
+ -- Return the generate functions
+ cellGn = AST.GenerateSm cellLabel cellGenScheme [] [compins,assign]
+-}
+-----------------------------------------------------------------------------
+-- Function to generate VHDL for applications
+-----------------------------------------------------------------------------
+genApplication ::
+ (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
+ -> CoreSyn.CoreBndr -- ^ The function to apply
+ -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
+ -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements
+genApplication dst f args =
+ case Var.globalIdVarDetails f of
+ IdInfo.DataConWorkId dc -> case dst of
+ -- It's a datacon. Create a record from its arguments.
+ Left bndr -> do
+ -- We have the bndr, so we can get at the type
+ labels <- getFieldLabels (Var.varType bndr)
+ return $ zipWith mkassign labels $ map (either exprToVHDLExpr id) args
+ where
+ mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
+ mkassign label arg =
+ let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
+ mkUncondAssign (Right sel_name) arg
+ Right _ -> error $ "Generate.genApplication Can't generate dataconstructor application without an original binder"
+ IdInfo.VanillaGlobal -> do
+ -- It's a global value imported from elsewhere. These can be builtin
+ -- functions. Look up the function name in the name table and execute
+ -- the associated builder if there is any and the argument count matches
+ -- (this should always be the case if it typechecks, but just to be
+ -- sure...).
+ case (Map.lookup (varToString f) globalNameTable) of
+ Just (arg_count, builder) ->
+ if length args == arg_count then
+ builder dst f args
+ else
+ error $ "Generate.genApplication Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
+ Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
+ IdInfo.NotGlobalId -> do
+ signatures <- getA vsSignatures
+ -- This is a local id, so it should be a function whose definition we
+ -- have and which can be turned into a component instantiation.
+ let
+ signature = Maybe.fromMaybe
+ (error $ "Using function '" ++ (varToString f) ++ "' without signature? This should not happen!")
+ (Map.lookup f signatures)
+ entity_id = ent_id signature
+ -- TODO: Using show here isn't really pretty, but we'll need some
+ -- unique-ish value...
+ label = "comp_ins_" ++ (either show show) dst
+ portmaps = mkAssocElems (map (either exprToVHDLExpr id) args) ((either varToVHDLName id) dst) signature
+ in
+ return [mkComponentInst label entity_id portmaps]
+ details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details