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Generate VHDL for UncondDefs.
[matthijs/master-project/cλash.git]
/
FlattenTypes.hs
diff --git
a/FlattenTypes.hs
b/FlattenTypes.hs
index af6289e6588371855c1dc0ef6ef8be838c73fc5a..c7db378ef27279f1ef7519f458df5de78426f0e8 100644
(file)
--- a/
FlattenTypes.hs
+++ b/
FlattenTypes.hs
@@
-20,7
+20,7
@@
type SignalMap = HsValueMap SignalId
type StateId = Int
-- | How is a given (single) value in a function's type (ie, argument or
type StateId = Int
-- | How is a given (single) value in a function's type (ie, argument or
--- return value) used?
+--
return value) used?
data HsValueUse =
Port -- ^ Use it as a port (input or output)
| State StateId -- ^ Use it as state (input or output). The int is used to
data HsValueUse =
Port -- ^ Use it as a port (input or output)
| State StateId -- ^ Use it as state (input or output). The int is used to
@@
-176,3
+176,10
@@
genSignalId use ty = do
let s = (n, SignalInfo Nothing use ty)
State.put (defs, s:sigs, n+1)
return n
let s = (n, SignalInfo Nothing use ty)
State.put (defs, s:sigs, n+1)
return n
+
+-- | Returns the SignalInfo for the given signal. Errors if the signal is not
+-- known in the session.
+getSignalInfo :: SignalId -> FlattenState SignalInfo
+getSignalInfo id = do
+ (defs, sigs, n) <- State.get
+ return $ signalInfo sigs id