m = init_mem_mapping(EVEN_STAGE);\r
init_input_addresses_regular(m, EVEN_STAGE);\r
/* do_half_regular_stage will init output addresses */\r
next_cycle();\r
do_half_regular_stage(m, EVEN_STAGE, FIRST_HALF);\r
do_half_regular_stage(m, EVEN_STAGE, SECOND_HALF);\r
m = init_mem_mapping(EVEN_STAGE);\r
init_input_addresses_regular(m, EVEN_STAGE);\r
/* do_half_regular_stage will init output addresses */\r
next_cycle();\r
do_half_regular_stage(m, EVEN_STAGE, FIRST_HALF);\r
do_half_regular_stage(m, EVEN_STAGE, SECOND_HALF);\r