- /* We need to do n_t regular stages. Since we do two stages each\r
- * iteration, we'll do n_t / 2 iterations (and a -1 because we check after looping) */\r
- init_loop(LC1, (PARAM_n_t / 2) - 1);\r
- do {\r
- m = init_mem_mapping(EVEN_STAGE);\r
- init_input_addresses_regular(m, EVEN_STAGE);\r
- /* do_half_regular_stage will init output addresses */\r
- next_cycle();\r
- do_half_regular_stage(m, EVEN_STAGE, FIRST_HALF);\r
- do_half_regular_stage(m, EVEN_STAGE, SECOND_HALF);\r
- stage++;\r
- next_cycle();\r
- init_input_addresses_regular(m, ODD_STAGE);\r
- m = init_mem_mapping(ODD_STAGE);\r
- next_cycle();\r
- do_half_regular_stage(m, ODD_STAGE, FIRST_HALF);\r
- do_half_regular_stage(m, ODD_STAGE, SECOND_HALF);\r
- stage++;\r
- } while (loop_next(LC1));\r