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Split off the VHDL type generating code.
[matthijs/master-project/cλash.git]
/
CoreTools.hs
diff --git
a/CoreTools.hs
b/CoreTools.hs
index 4cafec1b34f8225870b4cb6b32af8ee03505936a..73904b935f7b266b8be6e84c7553287d91a60c22 100644
(file)
--- a/
CoreTools.hs
+++ b/
CoreTools.hs
@@
-119,6
+119,11
@@
is_var :: CoreSyn.CoreExpr -> Bool
is_var (CoreSyn.Var _) = True
is_var _ = False
is_var (CoreSyn.Var _) = True
is_var _ = False
+-- Can the given core expression be applied to something? This is true for
+-- applying to a value as well as a type.
+is_applicable :: CoreSyn.CoreExpr -> Bool
+is_applicable expr = is_fun expr || is_poly expr
+
-- Does the given CoreExpr have any free type vars?
has_free_tyvars :: CoreSyn.CoreExpr -> Bool
has_free_tyvars = not . VarSet.isEmptyVarSet . (CoreFVs.exprSomeFreeVars Var.isTyVar)
-- Does the given CoreExpr have any free type vars?
has_free_tyvars :: CoreSyn.CoreExpr -> Bool
has_free_tyvars = not . VarSet.isEmptyVarSet . (CoreFVs.exprSomeFreeVars Var.isTyVar)