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Remove getDesignFiles from the VHDLState monad.
[matthijs/master-project/cλash.git]
/
Bits.hs
diff --git
a/Bits.hs
b/Bits.hs
index 99131d063ceffb834d2eec05451fac449feaf38b..50f6aa4c3f6766749e0a6e590080f62437c78591 100644
(file)
--- a/
Bits.hs
+++ b/
Bits.hs
@@
-1,5
+1,10
@@
+{-# LANGUAGE FlexibleContexts,GADTs,ExistentialQuantification,LiberalTypeSynonyms #-}
+
module Bits where
module Bits where
+import qualified Data.Param.FSVec as FSVec
+import qualified Data.TypeLevel as TypeLevel
+
--class Signal a where
-- hwand :: a -> a -> a
-- hwor :: a -> a -> a
--class Signal a where
-- hwand :: a -> a -> a
-- hwor :: a -> a -> a
@@
-53,4
+58,8
@@
type Stream a = [a]
lows = Low : lows
highs = High : highs
lows = Low : lows
highs = High : highs
+dontcare = undefined
+
+type BitVec len = FSVec.FSVec len Bit
+
-- vim: set ts=8 sw=2 sts=2 expandtab:
-- vim: set ts=8 sw=2 sts=2 expandtab: