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Never inline the half_adder function.
[matthijs/master-project/cλash.git]
/
Alu.hs
diff --git
a/Alu.hs
b/Alu.hs
index b888fc9dca18419523a4b33234c6e8e900d083ac..ea9bae8cd551db729f16850f0146b7a756c64197 100644
(file)
--- a/
Alu.hs
+++ b/
Alu.hs
@@
-1,26
+1,29
@@
-module Alu
(main)
where
+module Alu where
import Bits
import qualified Sim
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
import Bits
import qualified Sim
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
+dontcare = DontCare
+
program = [
-- (addr, we, op)
(High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
(Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
program = [
-- (addr, we, op)
(High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
(Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
- (Low, High,
DontC
are), -- r0 = z (1)
+ (Low, High,
dontc
are), -- r0 = z (1)
(High, Low, High), -- z = r1 and t (0); t = r1 (1)
(High, Low, High), -- z = r1 and t (0); t = r1 (1)
- (High, High,
DontC
are) -- r1 = z (0)
+ (High, High,
dontc
are) -- r1 = z (0)
]
]
-initial_state = (Regs Low High, Low, Low)
+--initial_state = (Regs Low High, Low, Low)
+initial_state = ((Low, High), Low, Low)
-- Register bank
type RegAddr = Bit
-- Register bank
type RegAddr = Bit
-
--
type RegisterBankState = (Bit, Bit)
-data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+type RegisterBankState = (Bit, Bit)
+
--
data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
register_bank ::
(RegAddr, Bit, Bit) -> -- (addr, we, d)
register_bank ::
(RegAddr, Bit, Bit) -> -- (addr, we, d)
@@
-28,45
+31,41
@@
register_bank ::
(RegisterBankState, Bit) -- (s', o)
register_bank (Low, Low, _) s = -- Read r0
(RegisterBankState, Bit) -- (s', o)
register_bank (Low, Low, _) s = -- Read r0
- (s, r0 s)
+ --(s, r0 s)
+ (s, fst s)
register_bank (High, Low, _) s = -- Read r1
register_bank (High, Low, _) s = -- Read r1
- (s, r1 s)
+ --(s, r1 s)
+ (s, snd s)
register_bank (addr, High, d) s = -- Write
register_bank (addr, High, d) s = -- Write
- (s',
DontC
are)
+ (s',
dontc
are)
where
where
- Regs r0 r1 = s
- r0' = if addr == Low then d else r0
- r1' = if addr == High then d else r1
- s' = Regs r0' r1'
+ --Regs r0 r1 = s
+ (r0, r1) = s
+ r0' = case addr of Low -> d; High -> r0; otherwise -> dontcare
+ r1' = case addr of High -> d; Low -> r1; otherwise -> dontcare
+ --s' = Regs r0' r1'
+ s' = (r0', r1')
-- ALU
type AluOp = Bit
-- ALU
type AluOp = Bit
-alu ::
(AluOp, Bit, Bit)
-> Bit
-alu
(High, a, b)
= a `hwand` b
-alu
(Low, a, b)
= a `hwor` b
+alu ::
AluOp -> Bit -> Bit
-> Bit
+alu
High a b
= a `hwand` b
+alu
Low a b
= a `hwor` b
type ExecState = (RegisterBankState, Bit, Bit)
type ExecState = (RegisterBankState, Bit, Bit)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, (
Bit
))
-- Read & Exec
-- Read & Exec
-exec (addr,
Low
, op) s =
- (s',
()
)
+exec (addr,
we
, op) s =
+ (s',
z'
)
where
(reg_s, t, z) = s
where
(reg_s, t, z) = s
- (reg_s', t') = register_bank (addr,
Low, DontCare
) reg_s
- z' = alu
(op, t', t)
+ (reg_s', t') = register_bank (addr,
we, z
) reg_s
+ z' = alu
op t' t
s' = (reg_s', t', z')
s' = (reg_s', t', z')
--- Write
-exec (addr, High, op) s =
- (s', ())
- where
- (reg_s, t, z) = s
- (reg_s', _) = register_bank (addr, High, z) reg_s
- s' = (reg_s', t, z)
-
-- vim: set ts=8 sw=2 sts=2 expandtab:
-- vim: set ts=8 sw=2 sts=2 expandtab: