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Be more strict in state recognition.
[matthijs/master-project/cλash.git]
/
Alu.hs
diff --git
a/Alu.hs
b/Alu.hs
index edb4d1a7440d63b9447ec7264fdc2595700cdd8a..e1aff99e98bbafc444ef29035dcaed1c2817781f 100644
(file)
--- a/
Alu.hs
+++ b/
Alu.hs
@@
-30,6
+30,7
@@
type RegAddr = Bit
type RegisterBankState = State (Word, Word)
--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
type RegisterBankState = State (Word, Word)
--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+{-# NOINLINE register_bank #-}
register_bank ::
RegAddr -- ^ Address
-> Bit -- ^ Write Enable
register_bank ::
RegAddr -- ^ Address
-> Bit -- ^ Write Enable