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Let the exec function output something.
[matthijs/master-project/cλash.git]
/
Alu.hs
diff --git
a/Alu.hs
b/Alu.hs
index e9ddf5775869a4538ee064b120d0034e8730cf82..ca2dbe9180613a3db75b55843660299246f809aa 100644
(file)
--- a/
Alu.hs
+++ b/
Alu.hs
@@
-5,7
+5,7
@@
import qualified Sim
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
-dontcare =
Low
+dontcare =
DontCare
program = [
-- (addr, we, op)
program = [
-- (addr, we, op)
@@
-43,8
+43,8
@@
register_bank (addr, High, d) s = -- Write
where
--Regs r0 r1 = s
(r0, r1) = s
where
--Regs r0 r1 = s
(r0, r1) = s
- r0' =
if addr == Low then d else r0
- r1' =
if addr == High then d else r1
+ r0' =
case addr of Low -> d; High -> r0; otherwise -> dontcare
+ r1' =
case addr of High -> d; Low -> r1; otherwise -> dontcare
--s' = Regs r0' r1'
s' = (r0', r1')
--s' = Regs r0' r1'
s' = (r0', r1')
@@
-61,11
+61,11
@@
salu High a b s = (s, a `hwand` b)
salu Low a b s = (s, a `hwor` b)
type ExecState = (RegisterBankState, Bit, Bit)
salu Low a b s = (s, a `hwor` b)
type ExecState = (RegisterBankState, Bit, Bit)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, (
Bit
))
-- Read & Exec
exec (addr, Low, op) s =
-- Read & Exec
exec (addr, Low, op) s =
- (s',
()
)
+ (s',
z'
)
where
(reg_s, t, z) = s
(reg_s', t') = register_bank (addr, Low, dontcare) reg_s
where
(reg_s, t, z) = s
(reg_s', t') = register_bank (addr, Low, dontcare) reg_s
@@
-74,7
+74,7
@@
exec (addr, Low, op) s =
-- Write
exec (addr, High, op) s =
-- Write
exec (addr, High, op) s =
- (s',
()
)
+ (s',
dontcare
)
where
(reg_s, t, z) = s
(reg_s', _) = register_bank (addr, High, z) reg_s
where
(reg_s, t, z) = s
(reg_s', _) = register_bank (addr, High, z) reg_s