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We now make a show function for all default datatypes.
[matthijs/master-project/cλash.git]
/
Alu.hs
diff --git
a/Alu.hs
b/Alu.hs
index 0fba3406d9bf55dfb532f93d46144adf58c988cc..b3d5b220f13970bc123ccafd776dab62ffa483dd 100644
(file)
--- a/
Alu.hs
+++ b/
Alu.hs
@@
-1,6
+1,8
@@
module Alu where
import Bits
import qualified Sim
module Alu where
import Bits
import qualified Sim
+import Data.SizedWord
+import Types
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
@@
-17,18
+19,18
@@
program = [
]
--initial_state = (Regs Low High, Low, Low)
]
--initial_state = (Regs Low High, Low, Low)
-initial_state = ((
Low, High), Low, Low
)
+initial_state = ((
0, 1), 0, 0
)
+type Word = SizedWord D4
-- Register bank
-- Register bank
-
type RegAddr = Bit
type RegAddr = Bit
-type RegisterBankState = (
Bit, Bit
)
+type RegisterBankState = (
Word, Word
)
--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
register_bank ::
--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
register_bank ::
- (RegAddr, Bit,
Bit
) -> -- (addr, we, d)
+ (RegAddr, Bit,
Word
) -> -- (addr, we, d)
RegisterBankState -> -- s
RegisterBankState -> -- s
- (RegisterBankState,
Bit
) -- (s', o)
+ (RegisterBankState,
Word
) -- (s', o)
register_bank (Low, Low, _) s = -- Read r0
--(s, r0 s)
register_bank (Low, Low, _) s = -- Read r0
--(s, r0 s)
@@
-39,7
+41,7
@@
register_bank (High, Low, _) s = -- Read r1
(s, snd s)
register_bank (addr, High, d) s = -- Write
(s, snd s)
register_bank (addr, High, d) s = -- Write
- (s',
dontcare
)
+ (s',
0
)
where
--Regs r0 r1 = s
(r0, r1) = s
where
--Regs r0 r1 = s
(r0, r1) = s
@@
-52,12
+54,15
@@
register_bank (addr, High, d) s = -- Write
type AluOp = Bit
type AluOp = Bit
-alu :: AluOp -> Bit -> Bit -> Bit
-alu High a b = a `hwand` b
-alu Low a b = a `hwor` b
+alu :: AluOp -> Word -> Word -> Word
+{-# NOINLINE alu #-}
+--alu High a b = a `hwand` b
+--alu Low a b = a `hwor` b
+alu High a b = a + b
+alu Low a b = a - b
-type ExecState = (RegisterBankState,
Bit, Bit
)
-exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState,
(Bit)
)
+type ExecState = (RegisterBankState,
Word, Word
)
+exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState,
Word
)
-- Read & Exec
exec (addr, we, op) s =
-- Read & Exec
exec (addr, we, op) s =