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Remove the DontCare value from the Bit type.
[matthijs/master-project/cλash.git]
/
Alu.hs
diff --git
a/Alu.hs
b/Alu.hs
index b888fc9dca18419523a4b33234c6e8e900d083ac..78c5afcfe5504c8747aeb314d45511b4a79a8cc2 100644
(file)
--- a/
Alu.hs
+++ b/
Alu.hs
@@
-1,17
+1,19
@@
-module Alu
(main)
where
+module Alu where
import Bits
import qualified Sim
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
import Bits
import qualified Sim
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
+dontcare = Low
+
program = [
-- (addr, we, op)
(High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
(Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
program = [
-- (addr, we, op)
(High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
(Low, Low, Low), -- z = r0 or t (1); t = r0 (0)
- (Low, High,
DontC
are), -- r0 = z (1)
+ (Low, High,
dontc
are), -- r0 = z (1)
(High, Low, High), -- z = r1 and t (0); t = r1 (1)
(High, Low, High), -- z = r1 and t (0); t = r1 (1)
- (High, High,
DontC
are) -- r1 = z (0)
+ (High, High,
dontc
are) -- r1 = z (0)
]
initial_state = (Regs Low High, Low, Low)
]
initial_state = (Regs Low High, Low, Low)
@@
-34,7
+36,7
@@
register_bank (High, Low, _) s = -- Read r1
(s, r1 s)
register_bank (addr, High, d) s = -- Write
(s, r1 s)
register_bank (addr, High, d) s = -- Write
- (s',
DontC
are)
+ (s',
dontc
are)
where
Regs r0 r1 = s
r0' = if addr == Low then d else r0
where
Regs r0 r1 = s
r0' = if addr == Low then d else r0
@@
-45,9
+47,9
@@
register_bank (addr, High, d) s = -- Write
type AluOp = Bit
type AluOp = Bit
-alu ::
(AluOp, Bit, Bit)
-> Bit
-alu
(High, a, b)
= a `hwand` b
-alu
(Low, a, b)
= a `hwor` b
+alu ::
AluOp -> Bit -> Bit
-> Bit
+alu
High a b
= a `hwand` b
+alu
Low a b
= a `hwor` b
type ExecState = (RegisterBankState, Bit, Bit)
exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
type ExecState = (RegisterBankState, Bit, Bit)
exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, ())
@@
-57,8
+59,8
@@
exec (addr, Low, op) s =
(s', ())
where
(reg_s, t, z) = s
(s', ())
where
(reg_s, t, z) = s
- (reg_s', t') = register_bank (addr, Low,
DontC
are) reg_s
- z' = alu
(op, t', t)
+ (reg_s', t') = register_bank (addr, Low,
dontc
are) reg_s
+ z' = alu
op t' t
s' = (reg_s', t', z')
-- Write
s' = (reg_s', t', z')
-- Write