- (RegAddr, Bit, Bit) -> -- (addr, we, d)
- RegisterBankState -> -- s
- (RegisterBankState, Bit) -- (s', o)
-
-register_bank (Low, Low, _) s = -- Read r0
- --(s, r0 s)
- (s, fst s)
-
-register_bank (High, Low, _) s = -- Read r1
- --(s, r1 s)
- (s, snd s)
+ RegAddr -- ^ Address
+ -> Bit -- ^ Write Enable
+ -> Word -- ^ Data
+ -> RegisterBankState -> -- State
+ (RegisterBankState, Word) -- (State', Output)