- (RegAddr, Bit, Bit) -> -- (addr, we, d)
- RegisterBankState -> -- s
- (RegisterBankState, Bit) -- (s', o)
-
-register_bank (Low, Low, _) s = -- Read r0
- (s, r0 s)
-
-register_bank (High, Low, _) s = -- Read r1
- (s, r1 s)
-
-register_bank (addr, High, d) s = -- Write
- (s', DontCare)
- where
- Regs r0 r1 = s
- r0' = if addr == Low then d else r0
- r1' = if addr == High then d else r1
- s' = Regs r0' r1'
+ RegAddr -- ^ Address
+ -> Bit -- ^ Write Enable
+ -> Word -- ^ Data
+ -> RegisterBankState -> -- State
+ (RegisterBankState, Word) -- (State', Output)
+
+register_bank addr we d (State s) =
+ case we of
+ Low -> -- Read
+ let
+ o = case addr of Low -> fst s; High -> snd s
+ in (State s, o) -- Don't change state
+ High -> -- Write
+ let
+ (r0, r1) = s
+ r0' = case addr of Low -> d; High -> r0
+ r1' = case addr of High -> d; Low -> r1
+ s' = (r0', r1')
+ in (State s', 0) -- Don't output anything useful