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Set VHDL types based on Haskell Types.
[matthijs/master-project/cλash.git]
/
Adders.hs
diff --git
a/Adders.hs
b/Adders.hs
index 03f04101ff9c72612bea6e4ab5030bc8b9fc2eda..f32f5d4f9fd89acaa71d4535c072dafeb5f78361 100644
(file)
--- a/
Adders.hs
+++ b/
Adders.hs
@@
-1,8
+1,9
@@
module Adders where
import Bits
module Adders where
import Bits
+import qualified Sim
import Language.Haskell.Syntax
import Language.Haskell.Syntax
-main
= do show_add exp_adder; show_add rec_adder;
+main
IO f = Sim.simulateIO (Sim.stateless f) ()
show_add f = do print ("Sum: " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
where
show_add f = do print ("Sum: " ++ (displaysigs s)); print ("Carry: " ++ (displaysig c))
where
@@
-42,8
+43,9
@@
half_adder (a, b) =
full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
full_adder (a, b, cin) = (s, c)
where
full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
full_adder (a, b, cin) = (s, c)
where
- s = a `hwxor` b `hwxor` cin
- c = a `hwand` b `hwor` (cin `hwand` (a `hwxor` b))
+ (s1, c1) = half_adder(a, b)
+ (s, c2) = half_adder(s1, cin)
+ c = c1 `hwor` c2
-- Four bit adder
-- Explicit version
-- Four bit adder
-- Explicit version