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Add a trivial "wire" hardware model.
[matthijs/master-project/cλash.git]
/
Adders.hs
diff --git
a/Adders.hs
b/Adders.hs
index c49ba810ce1ae4768ac2bd7efd673d1c198a0a28..748c06fdb73e50158297e887b07939cb57d3865e 100644
(file)
--- a/
Adders.hs
+++ b/
Adders.hs
@@
-1,4
+1,4
@@
-module Adders
(main, no_carry_adder)
where
+module Adders where
import Bits
import Language.Haskell.Syntax
import Bits
import Language.Haskell.Syntax
@@
-10,12
+10,22
@@
show_add f = do print ("Sum: " ++ (displaysigs s)); print ("Carry: " ++ (displ
b = [Low, Low, Low, High]
(s, c) = f (a, b)
b = [Low, Low, Low, High]
(s, c) = f (a, b)
--- Combinatoric no-carry adder
+-- Not really an adder, but this is nice minimal hardware description
+wire :: Bit -> Bit
+wire a = a
+
+-- Combinatoric stateless no-carry adder
-- A -> B -> S
no_carry_adder :: (Bit, Bit) -> Bit
no_carry_adder (a, b) = a `hwxor` b
-- A -> B -> S
no_carry_adder :: (Bit, Bit) -> Bit
no_carry_adder (a, b) = a `hwxor` b
--- Combinatoric (one-bit) full adder
+-- Combinatoric stateless half adder
+-- A -> B -> (S, C)
+half_adder :: (Bit, Bit) -> (Bit, Bit)
+half_adder (a, b) =
+ ( a `hwxor` b, a `hwand` b )
+
+-- Combinatoric stateless full adder
-- (A, B, C) -> (S, C)
full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
full_adder (a, b, cin) = (s, c)
-- (A, B, C) -> (S, C)
full_adder :: (Bit, Bit, Bit) -> (Bit, Bit)
full_adder (a, b, cin) = (s, c)