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Merge branch 'cλash' of http://git.stderr.nl/matthijs/projects/master-project
[matthijs/master-project/cλash.git]
/
Adders.hs
diff --git
a/Adders.hs
b/Adders.hs
index 2ee1de69534f144ab6f41d627fdfc7ce950e4f05..3afb82fae22e6ecebd6349ac23da944ebbec95f5 100644
(file)
--- a/
Adders.hs
+++ b/
Adders.hs
@@
-1,9
+1,16
@@
module Adders where
import Bits
import qualified Sim
module Adders where
import Bits
import qualified Sim
+
+import qualified Prelude as P
+import Prelude hiding (
+ null, length, head, tail, last, init, take, drop, (++), map, foldl, foldr,
+ zipWith, zip, unzip, concat, reverse, iterate )
+
import Language.Haskell.Syntax
import Language.Haskell.Syntax
-import qualified Data.TypeLevel as TypeLevel
-import qualified Data.Param.FSVec as FSVec
+import Types
+import Data.Param.TFVec
+import Data.RangedWord
mainIO f = Sim.simulateIO (Sim.stateless f) ()
mainIO f = Sim.simulateIO (Sim.stateless f) ()
@@
-12,7
+19,7
@@
mainIO f = Sim.simulateIO (Sim.stateless f) ()
stateless :: (i -> o) -> (i -> () -> ((), o))
stateless f = \i s -> (s, f i)
stateless :: (i -> o) -> (i -> () -> ((), o))
stateless f = \i s -> (s, f i)
-show_add f = do print ("Sum: "
++ (displaysigs s)); print ("Carry: "
++ (displaysig c))
+show_add f = do print ("Sum: "
P.++ (displaysigs s)); print ("Carry: " P.
++ (displaysig c))
where
a = [High, High, High, High]
b = [Low, Low, Low, High]
where
a = [High, High, High, High]
b = [Low, Low, Low, High]
@@
-26,10
+33,10
@@
mux2 High (a, b) = b
wire :: Bit -> Bit
wire a = a
wire :: Bit -> Bit
wire a = a
-bus :: (TypeLevel.Pos len) => BitVec len -> BitVec len
+
--
bus :: (TypeLevel.Pos len) => BitVec len -> BitVec len
bus v = v
bus v = v
-bus_4 :: BitVec TypeLevel.D4 -> BitVec TypeLevel.D4
+
--
bus_4 :: BitVec TypeLevel.D4 -> BitVec TypeLevel.D4
bus_4 v = v
{-
bus_4 v = v
{-
@@
-165,26
+172,44
@@
highordtest = \x ->
in
\c d -> op' d c
in
\c d -> op' d c
+functiontest :: TFVec D4 Bit -> TFVec D5 Bit -> RangedWord D3 -> RangedWord D4 -> (Bit, Bit)
+functiontest = \v1 v2 i1 i2 -> let r1 = v1!i1 ; r2 = v2!i2 in (r1,r2)
+
+xhwnot x = hwnot x
+
+maptest :: TFVec D4 Bit -> TFVec D4 Bit
+maptest = \v -> let r = map xhwnot v in r
+
+highordtest2 = \a b ->
+ case a of
+ High -> \c d -> d
+ Low -> let
+ op' :: Bit -> Bit -> Bit
+ op' = case b of
+ High -> \c d -> d
+ Low -> \c d -> c
+ in
+ \c d -> op' d c
-- Four bit adder, using the continous adder below
-- [a] -> [b] -> ([s], cout)
-- Four bit adder, using the continous adder below
-- [a] -> [b] -> ([s], cout)
-
--
con_adder_4 as bs =
-
--
([s3, s2, s1, s0], c)
-
--
where
-
-- ((s0, _):(s1, _):(s2, _):(s3, c):_) = con_adder (zip ((reverse as) ++ lows) ((reverse bs)
++ lows))
+con_adder_4 as bs =
+ ([s3, s2, s1, s0], c)
+ where
+
((s0, _):(s1, _):(s2, _):(s3, c):_) = con_adder (P.zip ((P.reverse as) P.++ lows) ((P.reverse bs) P.
++ lows))
-- Continuous sequential version
-- Stream a -> Stream b -> Stream (sum, cout)
-- Continuous sequential version
-- Stream a -> Stream b -> Stream (sum, cout)
-
--
con_adder :: Stream (Bit, Bit) -> Stream (Bit, Bit)
+con_adder :: Stream (Bit, Bit) -> Stream (Bit, Bit)
-- Forward to con_adder_int, but supply an initial state
-- Forward to con_adder_int, but supply an initial state
-
--
con_adder pin =
-
--
con_adder_int pin Low
+con_adder pin =
+ con_adder_int pin Low
-- Stream a -> Stream b -> state -> Stream (s, c)
-- Stream a -> Stream b -> state -> Stream (s, c)
-
--
con_adder_int :: Stream (Bit, Bit) -> Bit -> Stream (Bit, Bit)
-
--
con_adder_int ((a,b):rest) cin =
-
--
(s, cout) : con_adder_int rest cout
-
--
where
--- (s, cout) = full_adder a b cin
+con_adder_int :: Stream (Bit, Bit) -> Bit -> Stream (Bit, Bit)
+con_adder_int ((a,b):rest) cin =
+ (s, cout) : con_adder_int rest cout
+ where
+ (s, cout) = full_adder (a, b, cin)
-- vim: set ts=8 sw=2 sts=2 expandtab:
-- vim: set ts=8 sw=2 sts=2 expandtab: