+import qualified Sim
+
+import qualified Prelude as P
+import Prelude hiding (
+ null, length, head, tail, last, init, take, drop, (++), map, foldl, foldr,
+ zipWith, zip, unzip, concat, reverse, iterate )
+
+-- import Language.Haskell.Syntax
+import Types
+import Types.Data.Num.Decimal.Literals
+import Data.Param.TFVec
+import Data.RangedWord
+import Data.SizedInt
+import Data.SizedWord
+
+mainIO f = Sim.simulateIO (Sim.stateless f) ()
+
+-- This function is from Sim.hs, but we redefine it here so it can get inlined
+-- by default.
+stateless :: (i -> o) -> (i -> () -> ((), o))
+stateless f = \i s -> (s, f i)
+
+-- show_add f = do print ("Sum: " P.++ (displaysigs s)); print ("Carry: " P.++ (displaysig c))
+-- where
+-- a = [High, High, High, High]
+-- b = [Low, Low, Low, High]
+-- (s, c) = f (a, b)
+
+mux2 :: Bit -> (Bit, Bit) -> Bit
+mux2 Low (a, b) = a
+mux2 High (a, b) = b
+
+-- Not really an adder, but this is nice minimal hardware description
+wire :: Bit -> Bit
+wire a = a
+
+-- bus :: (TypeLevel.Pos len) => BitVec len -> BitVec len
+bus v = v
+
+-- bus_4 :: BitVec TypeLevel.D4 -> BitVec TypeLevel.D4
+bus_4 v = v
+
+{-
+inv_n :: (Pos len) => BitVec len -> BitVec len
+inv_n v =
+ --FSVec.map hwnot v
+ inv_n_rec v
+
+class Inv vec where
+ inv_n_rec :: vec -> vec
+
+instance (Pos len) => Inv (BitVec len) where
+ inv_n_rec v =
+ h FSVec.+> t
+ where
+ h = FSVec.head v
+ t = FSVec.tail v
+
+instance Inv (BitVec D0) where
+ inv_n_rec v = v
+-}
+-- Not really an adder either, but a slightly more complex example
+inv :: Bit -> Bit
+inv a = let r = hwnot a in r
+
+-- Not really an adder either, but a slightly more complex example
+invinv :: Bit -> Bit
+invinv a = hwnot (hwnot a)