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We now output VHDL types in the correct order
[matthijs/master-project/cλash.git]
/
Adders.hs
diff --git
a/Adders.hs
b/Adders.hs
index 672c83c964fe630f154a802bf2feb8160865ac0d..6ada7df0f58d522c73522df6a3014c8944eb047c 100644
(file)
--- a/
Adders.hs
+++ b/
Adders.hs
@@
-174,8
+174,8
@@
highordtest = \x ->
xand a b = hwand a b
xand a b = hwand a b
-functiontest :: TFVec D4 (TFVec D3 Bit) ->
TFVec D12 Bit
-functiontest = \v -> let r =
concat v
in r
+functiontest :: TFVec D4 (TFVec D3 Bit) ->
(TFVec D12 Bit, TFVec D3 Bit)
+functiontest = \v -> let r =
(concat v, head v)
in r
xhwnot x = hwnot x
xhwnot x = hwnot x