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@INPROCEEDINGS{Wired,
timestamp = {2010.01.20}
}
+@INPROCEEDINGS{reductioncircuit,
+ author = {M. E. T. Gerards and J. Kuper and A. B. J. Kokkeler and E. Molenkamp},
+ title = {Streaming Reduction Circuit},
+ booktitle = {Proceedings of the 12th EUROMICRO Conference on Digital System Design,
+ Architectures, Methods and Tools, Patras, Greece},
+ year = {2009},
+ pages = {287--292},
+ address = {Los Alamitos},
+ month = {August},
+ publisher = {IEEE Computer Society Press},
+ abstract = {Reduction circuits are used to reduce rows of ?oating point values
+ to single values. Binary ?oating point operators often have deep
+ pipelines, which may cause hazards when many consecutive rows have
+ to be reduced. We present an algorithm by which any number of consecutive
+ rows of arbitrary lengths can be reduced by a pipelined commutative
+ and associative binary operator in an efficient manner. The algorithm
+ is simple to implement, has a low latency, produces results in-order,
+ and requires only small buffers. Besides, it uses only a single pipeline
+ for the involved operation. The complexity of the algorithm depends
+ on the depth of the pipeline, not on the length of the input rows.
+ In this paper we discuss an implementation of this algorithm and
+ we prove its correctness.},
+ eprintid = {17041},
+ event_dates = {27-29 Aug 2009},
+ event_type = {Conference},
+ howpublished = {http://eprints.eemcs.utwente.nl/17041/},
+ id_number = {10.1109/DSD.2009.141},
+ international = {Yes},
+ isbn_13 = {978-0-7695-3782-5},
+ ispublished = {Published},
+ location = {Patras, Greece},
+ num_pages = {6},
+ official_url = {http://dx.doi.org/10.1109/DSD.2009.141},
+ owner = {baaijcpr},
+ pres_types = {Talk},
+ refereed = {Yes},
+ research_groups = {EWI-CAES: Computer Architecture for Embedded Systems},
+ research_programs = {CTIT-WiSe: Wireless and Sensor Systems},
+ research_projects = {EASY: Embedded Adaptive Streaming sYstems},
+ timestamp = {2010.02.26}
+}
+
@ARTICLE{reFLect,
author = {Grundy,Jim and Melham,Tom and O'Leary,John},
title = {{A reflective functional language for hardware design and theorem
timestamp = {2010.01.21}
}
+@BOOK{lambdacalculus,
+ title = {{The Lambda Calculus: its Syntax and Semantics}},
+ publisher = {{Elsevier Science}},
+ year = {1984},
+ author = {{H.P. Barendregt}},
+ volume = {103},
+ series = {{Studies in Logic and the Foundations of Mathematics}},
+ edition = {{Revised}},
+ owner = {baaijcpr},
+ timestamp = {2010.03.02}
+}
+
@INPROCEEDINGS{DAISY,
author = {Johnson, Steven D.},
title = {Applicative programming and digital design},
timestamp = {2010.01.20}
}
+@MASTERSTHESIS{HML3,
+ author = {Yanbing Li},
+ title = {{HML: An Innovative Hardware Description Language and Its Translation
+ to VHDL}},
+ school = {Cornell University},
+ year = {1995},
+ month = {August},
+ owner = {baaijcpr},
+ timestamp = {2010.03.08}
+}
+
@ARTICLE{HML2,
author = {Yanbing Li and Leeser, M.},
title = {{HML, a novel hardware description language and its translation to
timestamp = {2010.01.20}
}
+@MISC{polymorphism,
+ author = {Strachey, Christopher},
+ title = {Fundamental Concepts in Programming Languages},
+ howpublished = {Lecture Notes, International Summer School in Computer Programming,
+ Copenhagen},
+ month = August,
+ year = {1967},
+ note = {Reprinted in {\em Higher-Order and Symbolic Computation}, 13(1/2),
+ pp. 1--49, 2000},
+ owner = {baaijcpr},
+ timestamp = {2010.02.24}
+}
+
+@INPROCEEDINGS{Sulzmann2007,
+ author = {Sulzmann, Martin and Chakravarty, Manuel M. T. and Jones, Simon Peyton
+ and Donnelly, Kevin},
+ title = {{System F with Type Equality Coercions}},
+ booktitle = {{TLDI '07: Proceedings of the 2007 ACM SIGPLAN international workshop
+ on Types in languages design and implementation, Nice, France}},
+ year = {2007},
+ pages = {53--66},
+ address = {{New York, NY, USA}},
+ month = {January},
+ publisher = {{ACM}},
+ doi = {http://doi.acm.org/10.1145/1190315.1190324},
+ isbn = {1-59593-393-X},
+ location = {Nice, Nice, France},
+ owner = {darchon},
+ timestamp = {2009.10.23}
+}
+
+@ELECTRONIC{ghc,
+ author = {{The GHC Team}},
+ title = {{The Glasgow Haskell Compiler}},
+ url = {http://www.haskell.org/ghc/},
+ owner = {baaijcpr},
+ timestamp = {2010.02.25}
+}
+
+@BOOK{Haskell,
+ title = {{Haskell 98 language and libraries}},
+ year = {2003},
+ editor = {Simon Peyton Jones},
+ volume = {13},
+ number = {1},
+ pages = {1--255},
+ series = {{Journal of Functional Programming}},
+ booktitle = {{Journal of Functional Programming}},
+ journal = {Journal of Functional Programming},
+ owner = {darchon},
+ timestamp = {2010.01.29}
+}
+
@STANDARD{VHDL2008,
title = {{VHDL Language Reference Manual}},
organization = {IEEE},
timestamp = {2009.11.17}
}
-@comment{jabref-meta: selector_journal:}
+@STANDARD{Verilog,
+ title = {{Verilog Hardware Description Languages}},
+ organization = {{IEEE}},
+ number = {1365-2005},
+ year = {2005},
+ owner = {darchon},
+ timestamp = {2010.01.29}
+}
+
+@comment{jabref-meta: selector_publisher:}
@comment{jabref-meta: selector_author:}
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+@comment{jabref-meta: selector_journal:}
-@comment{jabref-meta: selector_publisher:}
+@comment{jabref-meta: selector_keywords:}