mapM addBuiltIn builtin_funcs
-- Create entities and architectures for them
Monad.zipWithM processBind statefuls binds
- modFuncs nameFlatFunction
- modFuncs VHDL.createEntity
- modFuncs VHDL.createArchitecture
- VHDL.getDesignFiles
+ modFuncMap $ Map.map (\fdata -> fdata {flatFunc = fmap nameFlatFunction (flatFunc fdata)})
+ modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcEntity = VHDL.createEntity hsfunc fdata})
+ funcs <- getFuncMap
+ modFuncMap $ Map.mapWithKey (\hsfunc fdata -> fdata {funcArch = VHDL.createArchitecture funcs hsfunc fdata})
+ funcs <- getFuncs
+ return $ VHDL.getDesignFiles (map snd funcs)
-- | Write the given design file to a file inside the given dir
-- The first library unit in the designfile must be an entity, whose name
propagateState hsfunc flatfunc =
flatfunc {flat_defs = apps', flat_sigs = sigs'}
where
- apps = filter is_FApp (flat_defs flatfunc)
(olds, news) = unzip $ getStateSignals hsfunc flatfunc
states' = zip olds news
-- Find all signals used by all sigdefs
-- Find the states whose "old state" signal is used only once
single_use_states = filter ((`notElem` multiple_uses) . fst) states'
-- See if these single use states can be propagated
- (substate_sigss, apps') = unzip $ map (propagateState' single_use_states) apps
+ (substate_sigss, apps') = unzip $ map (propagateState' single_use_states) (flat_defs flatfunc)
substate_sigs = concat substate_sigss
-- Mark any propagated state signals as SigSubState
sigs' = map
propagateState' ::
[(SignalId, SignalId)]
-- ^ TODO
- -> SigDef -- ^ The function application to process. Must be
- -- a FApp constructor.
+ -> SigDef -- ^ The SigDef to process.
-> ([SignalId], SigDef)
-- ^ Any signal ids that should become substates,
-- and the resulting application.
-propagateState' states app =
- (our_old ++ our_new, app {appFunc = hsfunc'})
+propagateState' states def =
+ if (is_FApp def) then
+ (our_old ++ our_new, def {appFunc = hsfunc'})
+ else
+ ([], def)
where
- hsfunc = appFunc app
- args = appArgs app
- res = appRes app
+ hsfunc = appFunc def
+ args = appArgs def
+ res = appRes def
our_states = filter our_state states
-- A state signal belongs in this function if the old state is
-- passed in, and the new state returned
-- | Adds signal names to the given FlatFunction
nameFlatFunction ::
- HsFunction
- -> FuncData
- -> VHDLState ()
+ FlatFunction
+ -> FlatFunction
-nameFlatFunction hsfunc fdata =
- let func = flatFunc fdata in
- case func of
- -- Skip (builtin) functions without a FlatFunction
- Nothing -> do return ()
- -- Name the signals in all other functions
- Just flatfunc ->
- let s = flat_sigs flatfunc in
- let s' = map nameSignal s in
- let flatfunc' = flatfunc { flat_sigs = s' } in
- setFlatFunc hsfunc flatfunc'
+nameFlatFunction flatfunc =
+ -- Name the signals
+ let
+ s = flat_sigs flatfunc
+ s' = map nameSignal s in
+ flatfunc { flat_sigs = s' }
where
nameSignal :: (SignalId, SignalInfo) -> (SignalId, SignalInfo)
nameSignal (id, info) =
setEntity hsfunc entity
where
hsfunc = HsFunction name (map useAsPort args) (useAsPort res)
- entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing
+ entity = Entity (VHDL.mkVHDLId name) (map toVHDLSignalMap args) (toVHDLSignalMap res) Nothing Nothing
builtin_funcs =
[