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Also allow uppercase letters and a period in VHDL ids.
[matthijs/master-project/cλash.git]
/
Pretty.hs
diff --git
a/Pretty.hs
b/Pretty.hs
index cb1f9fc7c1256900cb0476f0c993f43c953fdc3d..433c15a7abdc29914c2a6f84d0cd89a9f2cb2512 100644
(file)
--- a/
Pretty.hs
+++ b/
Pretty.hs
@@
-79,7
+79,7
@@
instance Pretty SignalExpr where
parens $ pPrint a <> text " = " <> pPrint b
instance Pretty SignalInfo where
- pPrint (SignalInfo name use ty) =
+ pPrint (SignalInfo name use ty
hints
) =
text ":" <> (pPrint use) <> (ppname name)
where
ppname Nothing = empty