-module Alu where
-import Bits
+module Alu where
import qualified Sim
-import Data.SizedWord
-import Types
+import CLasH.HardwareTypes hiding (fst,snd)
+import CLasH.Translator.Annotations
+import qualified Prelude as P
+
+fst (a, b) = a
+snd (a, b) = b
main = Sim.simulate exec program initial_state
mainIO = Sim.simulateIO exec initial_state
]
--initial_state = (Regs Low High, Low, Low)
-initial_state = ((0, 1), 0, 0)
+initial_state = State (State (0, 1), 0, 0)
type Word = SizedWord D4
-- Register bank
type RegAddr = Bit
-type RegisterBankState = (Word, Word)
+type RegisterBankState = State (Word, Word)
--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+{-# NOINLINE register_bank #-}
register_bank ::
- (RegAddr, Bit, Word) -> -- (addr, we, d)
- RegisterBankState -> -- s
- (RegisterBankState, Word) -- (s', o)
-
-register_bank (Low, Low, _) s = -- Read r0
- --(s, r0 s)
- (s, fst s)
-
-register_bank (High, Low, _) s = -- Read r1
- --(s, r1 s)
- (s, snd s)
+ RegAddr -- ^ Address
+ -> Bit -- ^ Write Enable
+ -> Word -- ^ Data
+ -> RegisterBankState -> -- State
+ (RegisterBankState, Word) -- (State', Output)
-register_bank (addr, High, d) s = -- Write
- (s', 0)
+register_bank addr we d (State s) = (State s', o)
where
- --Regs r0 r1 = s
- (r0, r1) = s
- r0' = case addr of Low -> d; High -> r0
- r1' = case addr of High -> d; Low -> r1
- --s' = Regs r0' r1'
- s' = (r0', r1')
+ s' = case we of
+ Low -> s -- Read
+ High -> -- Write
+ let
+ (r0, r1) = s
+ r0' = case addr of Low -> d; High -> r0
+ r1' = case addr of High -> d; Low -> r1
+ in (r0', r1')
+ o = case we of
+ -- Read
+ Low -> case addr of Low -> fst s; High -> snd s
+ -- Write
+ High -> 0 -- Don't output anything useful
-- ALU
alu High a b = a + b
alu Low a b = a - b
-type ExecState = (RegisterBankState, Word, Word)
+type ExecState = State (RegisterBankState, Word, Word)
exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)
+{-# ANN exec TopEntity #-}
-- Read & Exec
-exec (addr, we, op) s =
- (s', z')
+exec (addr, we, op) (State s) =
+ (State s', z')
where
(reg_s, t, z) = s
- (reg_s', t') = register_bank (addr, we, z) reg_s
+ (reg_s', t') = register_bank addr we z reg_s
z' = alu op t' t
s' = (reg_s', t', z')