type RegisterBankState = State (Word, Word)
--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+{-# NOINLINE register_bank #-}
register_bank ::
RegAddr -- ^ Address
-> Bit -- ^ Write Enable
{-# NOINLINE alu #-}
--alu High a b = a `hwand` b
--alu Low a b = a `hwor` b
-alu High a b = a P.+ b
-alu Low a b = a P.- b
+alu High a b = a + b
+alu Low a b = a - b
type ExecState = State (RegisterBankState, Word, Word)
exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)