-module Alu where
-import Bits
+module Alu where
import qualified Sim
-import Data.SizedWord
-import Types
-import Types.Data.Num
+import CLasH.HardwareTypes hiding (fst,snd)
import CLasH.Translator.Annotations
import qualified Prelude as P
dontcare = Low
-newtype State s = State s deriving (P.Show)
-
program = [
-- (addr, we, op)
(High, Low, High), -- z = r1 and t (0) ; t = r1 (1)
type RegisterBankState = State (Word, Word)
--data RegisterBankState = Regs { r0, r1 :: Bit} deriving (Show)
+{-# NOINLINE register_bank #-}
register_bank ::
RegAddr -- ^ Address
-> Bit -- ^ Write Enable
-> RegisterBankState -> -- State
(RegisterBankState, Word) -- (State', Output)
-register_bank addr we d (State s) =
- case we of
- Low -> -- Read
- let
- o = case addr of Low -> fst s; High -> snd s
- in (State s, o) -- Don't change state
- High -> -- Write
- let
- (r0, r1) = s
- r0' = case addr of Low -> d; High -> r0
- r1' = case addr of High -> d; Low -> r1
- s' = (r0', r1')
- in (State s', 0) -- Don't output anything useful
+register_bank addr we d (State s) = (State s', o)
+ where
+ s' = case we of
+ Low -> s -- Read
+ High -> -- Write
+ let
+ (r0, r1) = s
+ r0' = case addr of Low -> d; High -> r0
+ r1' = case addr of High -> d; Low -> r1
+ in (r0', r1')
+ o = case we of
+ -- Read
+ Low -> case addr of Low -> fst s; High -> snd s
+ -- Write
+ High -> 0 -- Don't output anything useful
-- ALU
{-# NOINLINE alu #-}
--alu High a b = a `hwand` b
--alu Low a b = a `hwor` b
-alu High a b = a P.+ b
-alu Low a b = a P.- b
+alu High a b = a + b
+alu Low a b = a - b
type ExecState = State (RegisterBankState, Word, Word)
exec :: (RegAddr, Bit, AluOp) -> ExecState -> (ExecState, Word)