import Bits
import qualified Sim
import Language.Haskell.Syntax
+import qualified Data.TypeLevel as TypeLevel
+import qualified Data.Param.FSVec as FSVec
mainIO f = Sim.simulateIO (Sim.stateless f) ()
wire :: Bit -> Bit
wire a = a
+bus :: (TypeLevel.Pos len) => BitVec len -> BitVec len
+bus v = v
+
+bus_4 :: BitVec TypeLevel.D4 -> BitVec TypeLevel.D4
+bus_4 v = v
+
+{-
+inv_n :: (Pos len) => BitVec len -> BitVec len
+inv_n v =
+ --FSVec.map hwnot v
+ inv_n_rec v
+
+class Inv vec where
+ inv_n_rec :: vec -> vec
+
+instance (Pos len) => Inv (BitVec len) where
+ inv_n_rec v =
+ h FSVec.+> t
+ where
+ h = FSVec.head v
+ t = FSVec.tail v
+
+instance Inv (BitVec D0) where
+ inv_n_rec v = v
+-}
-- Not really an adder either, but a slightly more complex example
inv :: Bit -> Bit
inv a = hwnot a
type ShifterState = (Bit, Bit, Bit, Bit)
shifter :: Bit -> ShifterState -> (ShifterState, Bit)
-shifter a s =
- (s', o)
+shifter i (a, b, c, d) =
+ (s', d)
+ where
+ s' = (i, a, b, c)
+
+{-# NOINLINE shifter_en #-}
+shifter_en :: Bit -> Bit-> ShifterState -> (ShifterState, Bit)
+shifter_en High i (a, b, c, d) =
+ (s', d)
+ where
+ s' = (i, a, b, c)
+
+shifter_en Low i s@(a, b, c, d) =
+ (s, d)
+
+-- Two multiplexed shifters
+type ShiftersState = (ShifterState, ShifterState)
+shifters :: Bit -> Bit -> ShiftersState -> (ShiftersState, Bit)
+shifters sel i (sa, sb) =
+ (s', out)
where
- s' = (a, b, c, d)
- (b, c, d, o) = s
+ (sa', outa) = shifter_en sel i sa
+ (sb', outb) = shifter_en (hwnot sel) i sb
+ s' = (sa', sb')
+ out = if sel == High then outa else outb
-- Combinatoric stateless no-carry adder
-- A -> B -> S