1 {-# LANGUAGE RelaxedPolyRec #-} -- Needed for vhdl_ty_either', for some reason...
2 module CLasH.VHDL.VHDLTools where
6 import qualified Data.Either as Either
7 import qualified Data.List as List
8 import qualified Data.Char as Char
9 import qualified Data.Map as Map
10 import qualified Control.Monad as Monad
11 import qualified Data.Accessor.Monad.Trans.State as MonadState
14 import qualified Language.VHDL.AST as AST
17 import qualified CoreSyn
19 import qualified OccName
22 import qualified TyCon
24 import qualified DataCon
25 import qualified CoreSubst
26 import qualified Outputable
29 import CLasH.VHDL.VHDLTypes
30 import CLasH.Translator.TranslatorTypes
31 import CLasH.Utils.Core.CoreTools
33 import CLasH.Utils.Pretty
34 import CLasH.VHDL.Constants
36 -----------------------------------------------------------------------------
37 -- Functions to generate concurrent statements
38 -----------------------------------------------------------------------------
40 -- Create an unconditional assignment statement
42 Either CoreSyn.CoreBndr AST.VHDLName -- ^ The signal to assign to
43 -> AST.Expr -- ^ The expression to assign
44 -> AST.ConcSm -- ^ The resulting concurrent statement
45 mkUncondAssign dst expr = mkAssign dst Nothing expr
47 -- Create a conditional assignment statement
49 Either CoreSyn.CoreBndr AST.VHDLName -- ^ The signal to assign to
50 -> AST.Expr -- ^ The condition
51 -> AST.Expr -- ^ The value when true
52 -> AST.Expr -- ^ The value when false
53 -> AST.ConcSm -- ^ The resulting concurrent statement
54 mkCondAssign dst cond true false = mkAssign dst (Just (cond, true)) false
56 -- Create a conditional or unconditional assignment statement
58 Either CoreSyn.CoreBndr AST.VHDLName -- ^ The signal to assign to
59 -> Maybe (AST.Expr , AST.Expr) -- ^ Optionally, the condition to test for
60 -- and the value to assign when true.
61 -> AST.Expr -- ^ The value to assign when false or no condition
62 -> AST.ConcSm -- ^ The resulting concurrent statement
63 mkAssign dst cond false_expr =
65 -- I'm not 100% how this assignment AST works, but this gets us what we
67 whenelse = case cond of
68 Just (cond_expr, true_expr) ->
70 true_wform = AST.Wform [AST.WformElem true_expr Nothing]
72 [AST.WhenElse true_wform cond_expr]
74 false_wform = AST.Wform [AST.WformElem false_expr Nothing]
75 dst_name = case dst of
76 Left bndr -> AST.NSimple (varToVHDLId bndr)
78 assign = dst_name AST.:<==: (AST.ConWforms whenelse false_wform Nothing)
83 Either CoreSyn.CoreBndr AST.VHDLName -- ^ The signal to assign to
84 -> [AST.Expr] -- ^ The conditions
85 -> [AST.Expr] -- ^ The expressions
86 -> AST.ConcSm -- ^ The Alt assigns
87 mkAltsAssign dst conds exprs
88 | (length conds) /= ((length exprs) - 1) = error "\nVHDLTools.mkAltsAssign: conditions expression mismatch"
91 whenelses = zipWith mkWhenElse conds exprs
92 false_wform = AST.Wform [AST.WformElem (last exprs) Nothing]
93 dst_name = case dst of
94 Left bndr -> AST.NSimple (varToVHDLId bndr)
96 assign = dst_name AST.:<==: (AST.ConWforms whenelses false_wform Nothing)
100 mkWhenElse :: AST.Expr -> AST.Expr -> AST.WhenElse
101 mkWhenElse cond true_expr =
103 true_wform = AST.Wform [AST.WformElem true_expr Nothing]
105 AST.WhenElse true_wform cond
108 [AST.Expr] -- ^ The argument that are applied to function
109 -> AST.VHDLName -- ^ The binder in which to store the result
110 -> Entity -- ^ The entity to map against.
111 -> [AST.AssocElem] -- ^ The resulting port maps
112 mkAssocElems args res entity =
113 arg_maps ++ (Maybe.maybeToList res_map_maybe)
115 arg_ports = ent_args entity
116 res_port_maybe = ent_res entity
117 -- Create an expression of res to map against the output port
118 res_expr = vhdlNameToVHDLExpr res
119 -- Map each of the input ports
120 arg_maps = zipWith mkAssocElem (map fst arg_ports) args
121 -- Map the output port, if present
122 res_map_maybe = fmap (\port -> mkAssocElem (fst port) res_expr) res_port_maybe
124 -- | Create an VHDL port -> signal association
125 mkAssocElem :: AST.VHDLId -> AST.Expr -> AST.AssocElem
126 mkAssocElem port signal = Just port AST.:=>: (AST.ADExpr signal)
128 -- | Create an aggregate signal
129 mkAggregateSignal :: [AST.Expr] -> AST.Expr
130 mkAggregateSignal x = AST.Aggregate (map (\z -> AST.ElemAssoc Nothing z) x)
133 String -- ^ The portmap label
134 -> AST.VHDLId -- ^ The entity name
135 -> [AST.AssocElem] -- ^ The port assignments
137 mkComponentInst label entity_id portassigns = AST.CSISm compins
139 -- We always have a clock port, so no need to map it anywhere but here
140 clk_port = mkAssocElem clockId (idToVHDLExpr clockId)
141 resetn_port = mkAssocElem resetId (idToVHDLExpr resetId)
142 compins = AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect (portassigns ++ [clk_port,resetn_port]))
144 -----------------------------------------------------------------------------
145 -- Functions to generate VHDL Exprs
146 -----------------------------------------------------------------------------
148 varToVHDLExpr :: Var.Var -> TypeSession AST.Expr
150 case Id.isDataConWorkId_maybe var of
151 -- This is a dataconstructor.
152 Just dc -> dataconToVHDLExpr dc
153 -- Not a datacon, just another signal.
154 Nothing -> return $ AST.PrimName $ AST.NSimple $ varToVHDLId var
156 -- Turn a VHDLName into an AST expression
157 vhdlNameToVHDLExpr = AST.PrimName
159 -- Turn a VHDL Id into an AST expression
160 idToVHDLExpr = vhdlNameToVHDLExpr . AST.NSimple
162 -- Turn a Core expression into an AST expression
163 exprToVHDLExpr core = varToVHDLExpr (exprToVar core)
165 -- Turn a String into a VHDL expr containing an id
166 stringToVHDLExpr :: String -> AST.Expr
167 stringToVHDLExpr = idToVHDLExpr . mkVHDLExtId
170 -- Turn a alternative constructor into an AST expression. For
171 -- dataconstructors, this is only the constructor itself, not any arguments it
172 -- has. Should not be called with a DEFAULT constructor.
173 altconToVHDLExpr :: CoreSyn.AltCon -> TypeSession AST.Expr
174 altconToVHDLExpr (CoreSyn.DataAlt dc) = dataconToVHDLExpr dc
176 altconToVHDLExpr (CoreSyn.LitAlt _) = error "\nVHDL.conToVHDLExpr: Literals not support in case alternatives yet"
177 altconToVHDLExpr CoreSyn.DEFAULT = error "\nVHDL.conToVHDLExpr: DEFAULT alternative should not occur here!"
179 -- Turn a datacon (without arguments!) into a VHDL expression.
180 dataconToVHDLExpr :: DataCon.DataCon -> TypeSession AST.Expr
181 dataconToVHDLExpr dc = do
182 typemap <- MonadState.get tsTypes
183 htype_either <- mkHTypeEither (DataCon.dataConRepType dc)
187 let dcname = DataCon.dataConName dc
189 (BuiltinType "Bit") -> return $ AST.PrimLit $ case Name.getOccString dcname of "High" -> "'1'"; "Low" -> "'0'"
190 (BuiltinType "Bool") -> return $ AST.PrimLit $ case Name.getOccString dcname of "True" -> "true"; "False" -> "false"
192 let existing_ty = Monad.liftM (fmap fst) $ Map.lookup htype typemap
195 let lit = idToVHDLExpr $ mkVHDLExtId $ Name.getOccString dcname
197 Nothing -> error $ "\nVHDLTools.dataconToVHDLExpr: Trying to make value for non-representable DataCon: " ++ pprString dc
198 -- Error when constructing htype
199 Left err -> error err
201 -----------------------------------------------------------------------------
202 -- Functions dealing with names, variables and ids
203 -----------------------------------------------------------------------------
205 -- Creates a VHDL Id from a binder
209 varToVHDLId var = mkVHDLExtId (varToString var ++ varToStringUniq var ++ show (lowers $ varToStringUniq var))
211 lowers :: String -> Int
212 lowers xs = length [x | x <- xs, Char.isLower x]
214 -- Creates a VHDL Name from a binder
218 varToVHDLName = AST.NSimple . varToVHDLId
220 -- Extracts the binder name as a String
224 varToString = OccName.occNameString . Name.nameOccName . Var.varName
226 -- Get the string version a Var's unique
227 varToStringUniq :: Var.Var -> String
228 varToStringUniq = show . Var.varUnique
230 -- Extracts the string version of the name
231 nameToString :: Name.Name -> String
232 nameToString = OccName.occNameString . Name.nameOccName
234 -- Shortcut for Basic VHDL Ids.
235 -- Can only contain alphanumerics and underscores. The supplied string must be
236 -- a valid basic id, otherwise an error value is returned. This function is
237 -- not meant to be passed identifiers from a source file, use mkVHDLExtId for
239 mkVHDLBasicId :: String -> AST.VHDLId
241 AST.unsafeVHDLBasicId $ (strip_multiscore . strip_leading . strip_invalid) s
243 -- Strip invalid characters.
244 strip_invalid = filter (`elem` ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ "_.")
245 -- Strip leading numbers and underscores
246 strip_leading = dropWhile (`elem` ['0'..'9'] ++ "_")
247 -- Strip multiple adjacent underscores
248 strip_multiscore = concatMap (\cs ->
254 -- Shortcut for Extended VHDL Id's. These Id's can contain a lot more
255 -- different characters than basic ids, but can never be used to refer to
257 -- Use extended Ids for any values that are taken from the source file.
258 mkVHDLExtId :: String -> AST.VHDLId
260 AST.unsafeVHDLExtId $ strip_invalid s
262 -- Allowed characters, taken from ForSyde's mkVHDLExtId
263 allowed = ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ " \"#&'()*+,./:;<=>_|!$%@?[]^`{}~-"
264 strip_invalid = filter (`elem` allowed)
266 -- Create a record field selector that selects the given label from the record
267 -- stored in the given binder.
268 mkSelectedName :: AST.VHDLName -> AST.VHDLId -> AST.VHDLName
269 mkSelectedName name label =
270 AST.NSelected $ name AST.:.: (AST.SSimple label)
272 -- Create an indexed name that selects a given element from a vector.
273 mkIndexedName :: AST.VHDLName -> AST.Expr -> AST.VHDLName
274 -- Special case for already indexed names. Just add an index
275 mkIndexedName (AST.NIndexed (AST.IndexedName name indexes)) index =
276 AST.NIndexed (AST.IndexedName name (indexes++[index]))
277 -- General case for other names
278 mkIndexedName name index = AST.NIndexed (AST.IndexedName name [index])
280 -----------------------------------------------------------------------------
281 -- Functions dealing with VHDL types
282 -----------------------------------------------------------------------------
283 builtin_types :: TypeMap
286 (BuiltinType "Bit", Just (std_logicTM, Nothing)),
287 (BuiltinType "Bool", Just (booleanTM, Nothing)) -- TysWiredIn.boolTy
290 -- Is the given type representable at runtime?
291 isReprType :: Type.Type -> TypeSession Bool
293 ty_either <- mkHTypeEither ty
294 return $ case ty_either of
298 -- | Turn a Core type into a HType, returning an error using the given
299 -- error string if the type was not representable.
300 mkHType :: (TypedThing t, Outputable.Outputable t) =>
301 String -> t -> TypeSession HType
303 htype_either <- mkHTypeEither ty
305 Right htype -> return htype
306 Left err -> error $ msg ++ err
308 -- | Turn a Core type into a HType. Returns either an error message if
309 -- the type was not representable, or the HType generated.
310 mkHTypeEither :: (TypedThing t, Outputable.Outputable t) =>
311 t -> TypeSession (Either String HType)
312 mkHTypeEither tything =
313 case getType tything of
314 Nothing -> return $ Left $ "\nVHDLTools.mkHTypeEither: Typed thing without a type: " ++ pprString tything
315 Just ty -> mkHTypeEither' ty
317 mkHTypeEither' :: Type.Type -> TypeSession (Either String HType)
318 mkHTypeEither' ty | ty_has_free_tyvars ty = return $ Left $ "\nVHDLTools.mkHTypeEither': Cannot create type: type has free type variables: " ++ pprString ty
319 | isStateType ty = return $ Right StateType
321 case Type.splitTyConApp_maybe ty of
322 Just (tycon, args) -> do
323 typemap <- MonadState.get tsTypes
324 let name = Name.getOccString (TyCon.tyConName tycon)
325 let builtinTyMaybe = Map.lookup (BuiltinType name) typemap
326 case builtinTyMaybe of
327 (Just x) -> return $ Right $ BuiltinType name
331 let el_ty = tfvec_elem ty
332 elem_htype_either <- mkHTypeEither el_ty
333 case elem_htype_either of
334 -- Could create element type
335 Right elem_htype -> do
336 len <- tfp_to_int (tfvec_len_ty ty)
337 return $ Right $ VecType len elem_htype
338 -- Could not create element type
339 Left err -> return $ Left $
340 "\nVHDLTools.mkHTypeEither': Can not construct vectortype for elementtype: " ++ pprString el_ty ++ err
342 len <- tfp_to_int (sized_word_len_ty ty)
343 return $ Right $ SizedWType len
345 len <- tfp_to_int (sized_word_len_ty ty)
346 return $ Right $ SizedIType len
348 bound <- tfp_to_int (ranged_word_bound_ty ty)
349 return $ Right $ RangedWType bound
351 mkTyConHType tycon args
352 Nothing -> return $ Left $ "\nVHDLTools.mkHTypeEither': Do not know what to do with type: " ++ pprString ty
354 mkTyConHType :: TyCon.TyCon -> [Type.Type] -> TypeSession (Either String HType)
355 mkTyConHType tycon args =
356 case TyCon.tyConDataCons tycon of
357 -- Not an algebraic type
358 [] -> return $ Left $ "VHDLTools.mkTyConHType: Only custom algebraic types are supported: " ++ pprString tycon
360 let arg_tyss = map DataCon.dataConRepArgTys dcs
361 let enum_ty = EnumType name (map (nameToString . DataCon.dataConName) dcs)
362 case (concat arg_tyss) of
363 -- No arguments, this is just an enumeration type
364 [] -> return (Right enum_ty)
365 -- At least one argument, this becomes an aggregate type
367 -- Resolve any type arguments to this type
368 let real_arg_tyss = map (map (CoreSubst.substTy subst)) arg_tyss
369 -- Remove any state type fields
370 let real_arg_tyss_nostate = map (filter (\x -> not (isStateType x))) real_arg_tyss
371 elem_htyss_either <- mapM (mapM mkHTypeEither) real_arg_tyss_nostate
372 let (errors, elem_htyss) = unzip (map Either.partitionEithers elem_htyss_either)
373 case (all null errors) of
374 True -> case (dcs, concat elem_htyss) of
375 -- A single constructor with a single (non-state) field?
376 ([dc], [elem_hty]) -> return $ Right elem_hty
377 -- If we get here, then all of the argument types were state
378 -- types (we check for enumeration types at the top). Not
379 -- sure how to handle this, so error out for now.
380 (_, []) -> error $ "ADT with only State elements (or something like that?) Dunno how to handle this yet. Tycon: " ++ pprString tycon ++ " Arguments: " ++ pprString args
381 -- A full ADT (with multiple fields and one or multiple
384 let (_, fieldss) = List.mapAccumL (List.mapAccumL label_field) labels elem_htyss
385 -- Only put in an enumeration as part of the aggregation
386 -- when there are multiple datacons
387 let enum_ty_part = case dcs of
389 _ -> Just ("constructor", enum_ty)
390 -- Create the AggrType HType
391 return $ Right $ AggrType name enum_ty_part fieldss
392 -- There were errors in element types
393 False -> return $ Left $
394 "\nVHDLTools.mkTyConHType: Can not construct type for: " ++ pprString tycon ++ "\n because no type can be construced for some of the arguments.\n"
395 ++ (concat $ concat errors)
397 name = (nameToString (TyCon.tyConName tycon))
398 tyvars = TyCon.tyConTyVars tycon
399 subst = CoreSubst.extendTvSubstList CoreSubst.emptySubst (zip tyvars args)
400 -- Label a field by taking the first available label and returning
402 label_field :: [String] -> HType -> ([String], (String, HType))
403 label_field (l:ls) htype = (ls, (l, htype))
404 labels = map (:[]) ['A'..'Z']
406 vhdlTy :: (TypedThing t, Outputable.Outputable t) =>
407 String -> t -> TypeSession (Maybe AST.TypeMark)
409 htype <- mkHType msg ty
412 -- | Translate a Haskell type to a VHDL type, generating a new type if needed.
413 -- Returns an error value, using the given message, when no type could be
414 -- created. Returns Nothing when the type is valid, but empty.
415 vhdlTyMaybe :: HType -> TypeSession (Maybe AST.TypeMark)
416 vhdlTyMaybe htype = do
417 typemap <- MonadState.get tsTypes
418 -- If not a builtin type, try the custom types
419 let existing_ty = Map.lookup htype typemap
421 -- Found a type, return it
422 Just (Just (t, _)) -> return $ Just t
423 Just (Nothing) -> return Nothing
424 -- No type yet, try to construct it
426 newty <- (construct_vhdl_ty htype)
427 MonadState.modify tsTypes (Map.insert htype newty)
429 Just (ty_id, ty_def) -> do
430 MonadState.modify tsTypeDecls (\typedefs -> typedefs ++ [mktydecl (ty_id, ty_def)])
432 Nothing -> return Nothing
434 -- Construct a new VHDL type for the given Haskell type. Returns an error
435 -- message or the resulting typemark and typedef.
436 construct_vhdl_ty :: HType -> TypeSession TypeMapRec
437 -- State types don't generate VHDL
438 construct_vhdl_ty htype =
440 StateType -> return Nothing
441 (SizedWType w) -> mkUnsignedTy w
442 (SizedIType i) -> mkSignedTy i
443 (RangedWType u) -> mkNaturalTy 0 u
444 (VecType n e) -> mkVectorTy (VecType n e)
445 -- Create a custom type from this tycon
446 otherwise -> mkTyconTy htype
448 -- | Create VHDL type for a custom tycon
449 mkTyconTy :: HType -> TypeSession TypeMapRec
452 (AggrType name enum_field_maybe fieldss) -> do
453 let (labelss, elem_htypess) = unzip (map unzip fieldss)
454 elemTyMaybess <- mapM (mapM vhdlTyMaybe) elem_htypess
455 let elem_tyss = map Maybe.catMaybes elemTyMaybess
456 case concat elem_tyss of
457 [] -> -- No non-empty fields
460 let reclabelss = map (map mkVHDLBasicId) labelss
461 let elemss = zipWith (zipWith AST.ElementDec) reclabelss elem_tyss
462 let elem_names = concatMap (concatMap prettyShow) elem_tyss
463 let ty_id = mkVHDLExtId $ name ++ elem_names
464 -- Find out if we need to add an extra field at the start of
465 -- the record type containing the constructor (only needed
466 -- when there's more than one constructor).
467 enum_ty_maybe <- case enum_field_maybe of
468 Nothing -> return Nothing
469 Just (_, enum_htype) -> do
470 enum_ty_maybe' <- vhdlTyMaybe enum_htype
471 case enum_ty_maybe' of
472 Nothing -> error $ "Couldn't translate enumeration type part of AggrType: " ++ show htype
473 -- Note that the first Just means the type is
474 -- translateable, while the second Just means that there
475 -- is a enum_ty at all (e.g., there's multiple
477 Just enum_ty -> return $ Just enum_ty
478 -- Create an record field declaration for the first
479 -- constructor field, if needed.
480 enum_dec_maybe <- case enum_field_maybe of
481 Nothing -> return $ Nothing
482 Just (enum_name, enum_htype) -> do
483 enum_vhdl_ty_maybe <- vhdlTyMaybe enum_htype
484 let enum_vhdl_ty = Maybe.fromMaybe (error $ "\nVHDLTools.mkTyconTy: Enumeration field should not have empty type: " ++ show enum_htype) enum_vhdl_ty_maybe
485 return $ Just $ AST.ElementDec (mkVHDLBasicId enum_name) enum_vhdl_ty
486 -- Turn the maybe into a list, so we can prepend it.
487 let enum_decs = Maybe.maybeToList enum_dec_maybe
488 let enum_tys = Maybe.maybeToList enum_ty_maybe
489 let ty_def = AST.TDR $ AST.RecordTypeDef (enum_decs ++ concat elemss)
490 let tupshow = mkTupleShow (enum_tys ++ concat elem_tyss) ty_id
491 MonadState.modify tsTypeFuns $ Map.insert (htype, showIdString) (showId, tupshow)
492 return $ Just (ty_id, Just $ Left ty_def)
493 (EnumType tycon dcs) -> do
494 let elems = map mkVHDLExtId dcs
495 let ty_id = mkVHDLExtId tycon
496 let ty_def = AST.TDE $ AST.EnumTypeDef elems
497 let enumShow = mkEnumShow elems ty_id
498 MonadState.modify tsTypeFuns $ Map.insert (htype, showIdString) (showId, enumShow)
499 return $ Just (ty_id, Just $ Left ty_def)
500 otherwise -> error $ "\nVHDLTools.mkTyconTy: Called for HType that is neiter a AggrType or EnumType: " ++ show htype
502 -- | Create a VHDL vector type
504 HType -- ^ The Haskell type of the Vector
505 -> TypeSession TypeMapRec
506 -- ^ An error message or The typemark created.
508 mkVectorTy (VecType len elHType) = do
509 typesMap <- MonadState.get tsTypes
510 elTyTmMaybe <- vhdlTyMaybe elHType
513 let ty_id = mkVHDLExtId $ "vector-"++ (AST.fromVHDLId elTyTm) ++ "-0_to_" ++ (show len)
514 let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
515 let existing_uvec_ty = fmap (fmap fst) $ Map.lookup (UVecType elHType) typesMap
516 case existing_uvec_ty of
518 let ty_def = AST.SubtypeIn t (Just range)
519 return (Just (ty_id, Just $ Right ty_def))
521 let vec_id = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elTyTm)
522 let vec_def = AST.TDA $ AST.UnconsArrayDef [tfvec_indexTM] elTyTm
523 MonadState.modify tsTypes (Map.insert (UVecType elHType) (Just (vec_id, (Just $ Left vec_def))))
524 MonadState.modify tsTypeDecls (\typedefs -> typedefs ++ [mktydecl (vec_id, (Just $ Left vec_def))])
525 let vecShowFuns = mkVectorShow elTyTm vec_id
526 mapM_ (\(id, subprog) -> MonadState.modify tsTypeFuns $ Map.insert (UVecType elHType, id) ((mkVHDLExtId id), subprog)) vecShowFuns
527 let ty_def = AST.SubtypeIn vec_id (Just range)
528 return (Just (ty_id, Just $ Right ty_def))
529 -- Vector of empty elements becomes empty itself.
530 Nothing -> return Nothing
531 mkVectorTy htype = error $ "\nVHDLTools.mkVectorTy: Called for HType that is not a VecType: " ++ show htype
534 Int -- ^ The minimum bound (> 0)
535 -> Int -- ^ The maximum bound (> minimum bound)
536 -> TypeSession TypeMapRec
537 -- ^ An error message or The typemark created.
538 mkNaturalTy min_bound max_bound = do
539 let bitsize = floor (logBase 2 (fromInteger (toInteger max_bound)))
540 let ty_id = mkVHDLExtId $ "natural_" ++ (show min_bound) ++ "_to_" ++ (show max_bound)
541 let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit $ show min_bound) (AST.PrimLit $ show bitsize)]
542 let ty_def = AST.SubtypeIn unsignedTM (Just range)
543 return (Just (ty_id, Just $ Right ty_def))
546 Int -- ^ Haskell type of the unsigned integer
547 -> TypeSession TypeMapRec
548 mkUnsignedTy size = do
549 let ty_id = mkVHDLExtId $ "unsigned_" ++ show (size - 1)
550 let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (size - 1))]
551 let ty_def = AST.SubtypeIn unsignedTM (Just range)
552 return (Just (ty_id, Just $ Right ty_def))
555 Int -- ^ Haskell type of the signed integer
556 -> TypeSession TypeMapRec
558 let ty_id = mkVHDLExtId $ "signed_" ++ show (size - 1)
559 let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (size - 1))]
560 let ty_def = AST.SubtypeIn signedTM (Just range)
561 return (Just (ty_id, Just $ Right ty_def))
563 -- Finds the field labels and types for aggregation HType. Returns an
564 -- error on other types.
566 HType -- ^ The HType to get fields for
567 -> Int -- ^ The constructor to get fields for (e.g., 0
568 -- for the first constructor, etc.)
569 -> [(String, HType)] -- ^ A list of fields, with their name and type
570 getFields htype dc_i = case htype of
571 (AggrType name _ fieldss)
572 | dc_i >= 0 && dc_i < length fieldss -> fieldss!!dc_i
573 | otherwise -> error $ "Invalid constructor index: " ++ (show dc_i) ++ ". No such constructor in HType: " ++ (show htype)
574 _ -> error $ "Can't get fields from non-aggregate HType: " ++ show htype
576 -- Finds the field labels for an aggregation type, as VHDLIds.
578 HType -- ^ The HType to get field labels for
579 -> Int -- ^ The constructor to get fields for (e.g., 0
580 -- for the first constructor, etc.)
581 -> [AST.VHDLId] -- ^ The labels
582 getFieldLabels htype dc_i = ((map mkVHDLBasicId) . (map fst)) (getFields htype dc_i)
584 -- Finds the field label for the constructor field, if any.
585 getConstructorFieldLabel ::
588 getConstructorFieldLabel (AggrType _ (Just con) _) =
589 Just $ mkVHDLBasicId (fst con)
590 getConstructorFieldLabel (AggrType _ Nothing _) =
592 getConstructorFieldLabel htype =
593 error $ "Can't get constructor field label from non-aggregate HType: " ++ show htype
595 mktydecl :: (AST.VHDLId, Maybe (Either AST.TypeDef AST.SubtypeIn)) -> Maybe AST.PackageDecItem
596 mytydecl (_, Nothing) = Nothing
597 mktydecl (ty_id, Just (Left ty_def)) = Just $ AST.PDITD $ AST.TypeDec ty_id ty_def
598 mktydecl (ty_id, Just (Right ty_def)) = Just $ AST.PDISD $ AST.SubtypeDec ty_id ty_def
601 [AST.TypeMark] -- ^ type of each tuple element
602 -> AST.TypeMark -- ^ type of the tuple
604 mkTupleShow elemTMs tupleTM = AST.SubProgBody showSpec [] [showExpr]
606 tupPar = AST.unsafeVHDLBasicId "tup"
607 showSpec = AST.Function showId [AST.IfaceVarDec tupPar tupleTM] stringTM
608 showExpr = AST.ReturnSm (Just $
609 AST.PrimLit "'('" AST.:&: showMiddle AST.:&: AST.PrimLit "')'")
611 showMiddle = if null elemTMs then
614 foldr1 (\e1 e2 -> e1 AST.:&: AST.PrimLit "','" AST.:&: e2) $
615 map ((genExprFCall showId).
618 (AST.NSimple tupPar AST.:.:).
620 (take tupSize recordlabels)
621 recordlabels = map (\c -> mkVHDLBasicId [c]) ['A'..'Z']
622 tupSize = length elemTMs
628 mkEnumShow elemIds enumTM = AST.SubProgBody showSpec [] [showExpr]
630 enumPar = AST.unsafeVHDLBasicId "enum"
631 showSpec = AST.Function showId [AST.IfaceVarDec enumPar enumTM] stringTM
632 showExpr = AST.ReturnSm (Just $
633 AST.PrimLit (show $ tail $ init $ AST.fromVHDLId enumTM))
636 AST.TypeMark -- ^ elemtype
637 -> AST.TypeMark -- ^ vectype
638 -> [(String,AST.SubProgBody)]
639 mkVectorShow elemTM vectorTM =
640 [ (headId, AST.SubProgBody headSpec [] [headExpr])
641 , (tailId, AST.SubProgBody tailSpec [AST.SPVD tailVar] [tailExpr, tailRet])
642 , (showIdString, AST.SubProgBody showSpec [AST.SPSB doShowDef] [showRet])
645 vecPar = AST.unsafeVHDLBasicId "vec"
646 resId = AST.unsafeVHDLBasicId "res"
647 headSpec = AST.Function (mkVHDLExtId headId) [AST.IfaceVarDec vecPar vectorTM] elemTM
649 headExpr = AST.ReturnSm (Just (AST.PrimName $ AST.NIndexed (AST.IndexedName
650 (AST.NSimple vecPar) [AST.PrimLit "0"])))
651 vecSlice init last = AST.PrimName (AST.NSlice
654 (AST.ToRange init last)))
655 tailSpec = AST.Function (mkVHDLExtId tailId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
656 -- variable res : fsvec_x (0 to vec'length-2);
659 (AST.SubtypeIn vectorTM
660 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
661 [AST.ToRange (AST.PrimLit "0")
662 (AST.PrimName (AST.NAttribute $
663 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
664 (AST.PrimLit "2")) ]))
666 -- res AST.:= vec(1 to vec'length-1)
667 tailExpr = AST.NSimple resId AST.:= (vecSlice
669 (AST.PrimName (AST.NAttribute $
670 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
671 AST.:-: AST.PrimLit "1"))
672 tailRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
673 showSpec = AST.Function showId [AST.IfaceVarDec vecPar vectorTM] stringTM
674 doShowId = AST.unsafeVHDLExtId "doshow"
675 doShowDef = AST.SubProgBody doShowSpec [] [doShowRet]
676 where doShowSpec = AST.Function doShowId [AST.IfaceVarDec vecPar vectorTM]
679 -- when 0 => return "";
680 -- when 1 => return head(vec);
681 -- when others => return show(head(vec)) & ',' &
682 -- doshow (tail(vec));
685 AST.CaseSm (AST.PrimName (AST.NAttribute $
686 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))
687 [AST.CaseSmAlt [AST.ChoiceE $ AST.PrimLit "0"]
688 [AST.ReturnSm (Just $ AST.PrimLit "\"\"")],
689 AST.CaseSmAlt [AST.ChoiceE $ AST.PrimLit "1"]
690 [AST.ReturnSm (Just $
692 (genExprFCall (mkVHDLExtId headId) (AST.PrimName $ AST.NSimple vecPar)) )],
693 AST.CaseSmAlt [AST.Others]
694 [AST.ReturnSm (Just $
696 (genExprFCall (mkVHDLExtId headId) (AST.PrimName $ AST.NSimple vecPar)) AST.:&:
697 AST.PrimLit "','" AST.:&:
698 genExprFCall doShowId
699 (genExprFCall (mkVHDLExtId tailId) (AST.PrimName $ AST.NSimple vecPar)) ) ]]
700 -- return '<' & doshow(vec) & '>';
701 showRet = AST.ReturnSm (Just $ AST.PrimLit "'<'" AST.:&:
702 genExprFCall doShowId (AST.PrimName $ AST.NSimple vecPar) AST.:&:
705 mkBuiltInShow :: [AST.SubProgBody]
706 mkBuiltInShow = [ AST.SubProgBody showBitSpec [] [showBitExpr]
707 , AST.SubProgBody showBoolSpec [] [showBoolExpr]
708 , AST.SubProgBody showSingedSpec [] [showSignedExpr]
709 , AST.SubProgBody showUnsignedSpec [] [showUnsignedExpr]
710 -- , AST.SubProgBody showNaturalSpec [] [showNaturalExpr]
713 bitPar = AST.unsafeVHDLBasicId "s"
714 boolPar = AST.unsafeVHDLBasicId "b"
715 signedPar = AST.unsafeVHDLBasicId "sint"
716 unsignedPar = AST.unsafeVHDLBasicId "uint"
717 -- naturalPar = AST.unsafeVHDLBasicId "nat"
718 showBitSpec = AST.Function showId [AST.IfaceVarDec bitPar std_logicTM] stringTM
719 -- if s = '1' then return "'1'" else return "'0'"
720 showBitExpr = AST.IfSm (AST.PrimName (AST.NSimple bitPar) AST.:=: AST.PrimLit "'1'")
721 [AST.ReturnSm (Just $ AST.PrimLit "\"High\"")]
723 (Just $ AST.Else [AST.ReturnSm (Just $ AST.PrimLit "\"Low\"")])
724 showBoolSpec = AST.Function showId [AST.IfaceVarDec boolPar booleanTM] stringTM
725 -- if b then return "True" else return "False"
726 showBoolExpr = AST.IfSm (AST.PrimName (AST.NSimple boolPar))
727 [AST.ReturnSm (Just $ AST.PrimLit "\"True\"")]
729 (Just $ AST.Else [AST.ReturnSm (Just $ AST.PrimLit "\"False\"")])
730 showSingedSpec = AST.Function showId [AST.IfaceVarDec signedPar signedTM] stringTM
731 showSignedExpr = AST.ReturnSm (Just $
732 AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerId)
733 (AST.NIndexed $ AST.IndexedName (AST.NSimple imageId) [signToInt]) Nothing )
735 signToInt = genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple signedPar)
736 showUnsignedSpec = AST.Function showId [AST.IfaceVarDec unsignedPar unsignedTM] stringTM
737 showUnsignedExpr = AST.ReturnSm (Just $
738 AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerId)
739 (AST.NIndexed $ AST.IndexedName (AST.NSimple imageId) [unsignToInt]) Nothing )
741 unsignToInt = genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple unsignedPar)
742 -- showNaturalSpec = AST.Function showId [AST.IfaceVarDec naturalPar naturalTM] stringTM
743 -- showNaturalExpr = AST.ReturnSm (Just $
744 -- AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerId)
745 -- (AST.NIndexed $ AST.IndexedName (AST.NSimple imageId) [AST.PrimName $ AST.NSimple $ naturalPar]) Nothing )
748 genExprFCall :: AST.VHDLId -> AST.Expr -> AST.Expr
749 genExprFCall fName args =
750 AST.PrimFCall $ AST.FCall (AST.NSimple fName) $
751 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) [args]
753 genExprPCall2 :: AST.VHDLId -> AST.Expr -> AST.Expr -> AST.SeqSm
754 genExprPCall2 entid arg1 arg2 =
755 AST.ProcCall (AST.NSimple entid) $
756 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) [arg1,arg2]
758 mkSigDec :: CoreSyn.CoreBndr -> TranslatorSession (Maybe AST.SigDec)
760 let error_msg = "\nVHDL.mkSigDec: Can not make signal declaration for type: \n" ++ pprString bndr
761 type_mark_maybe <- MonadState.lift tsType $ vhdlTy error_msg (Var.varType bndr)
762 case type_mark_maybe of
763 Just type_mark -> return $ Just (AST.SigDec (varToVHDLId bndr) type_mark Nothing)
764 Nothing -> return Nothing
766 -- | Does the given thing have a non-empty type?
767 hasNonEmptyType :: (TypedThing t, Outputable.Outputable t) =>
768 t -> TranslatorSession Bool
769 hasNonEmptyType thing = MonadState.lift tsType $ isJustM (vhdlTy "hasNonEmptyType: Non representable type?" thing)