1 \subsection{Restrictions}
4 \frametitle{Too Restrictive?}
6 \item Is CλasH too restrictive given the fact that a designer can currently not define his own vector transformations, or recursive functions for that matter?
11 \frametitle{Too Restrictive?}
13 \item There is certainly room to increase expressivity. But we can already describe non-trivial design in CλasH.
14 \item Example: Reduction circuit
18 \subsection{Reduction circuit}
21 \frametitle{Reduction Circuit}
23 \column{0.5\textwidth}
25 \includegraphics[height=6.5cm]{reducer}
27 \column{0.5\textwidth}
29 \item Reduction circuit sums the floating-point values of each row in a matrix.
30 \item Non-trivial due to pipe-lined floating-point adder.
31 \item Largest restrictions are the fixed-size vectors.
38 \includegraphics[height=9cm]{reducerschematic}
44 \frametitle{FIFO Buffer}
48 fifo :: (State mem) (input, shift) =
49 (State mem', out1, out2)
51 out1 | length mem == 0 = NotValid
52 | otherwise = head mem
53 out2 | length mem < 2 = NotValid
54 | otherwise = head (tail mem)
55 mem' = drop shift mem ++ [input]
61 \frametitle{FIFO Buffer}
65 fifo :: (State (Fifo {..})) (inp, shift) =
66 ( State (Fifo { mem = mem'
72 ptr' = ptr - shift + 1
73 mem'' = replace mem ptr (Valid inp)
74 mem' | shift == 0 = mem''
75 | shift == 1 = (tail mem'') <+ NotValid
76 | otherwise = ((tail (tail mem'')
77 <+ NotValid) <+ NotValid)
79 out2 = head (tail mem)
85 \frametitle{FIFO Buffer}
87 \item Wish: Dynamically sized vectors
88 \item Reality: Statically sized vectors
93 \frametitle{Dynamically Sized Vectors}
95 \item Map all vectors to RAMs:
97 \item Store length separately, extra logic
98 \item What happens if size of the vector exceeds size of the size of the RAM?
100 \item Translate to (shift/circular) Buffers
102 \item Requires analysis of data-access
103 \item How do we determine maximum size?