1 module CLasH.VHDL.Generate where
4 import qualified Data.List as List
5 import qualified Data.Map as Map
6 import qualified Control.Monad as Monad
8 import qualified Data.Either as Either
10 import Data.Accessor.MonadState as MonadState
14 import qualified Language.VHDL.AST as AST
17 import qualified CoreSyn
21 import qualified IdInfo
22 import qualified Literal
24 import qualified TyCon
27 import CLasH.Translator.TranslatorTypes
28 import CLasH.VHDL.Constants
29 import CLasH.VHDL.VHDLTypes
30 import CLasH.VHDL.VHDLTools
31 import CLasH.Utils as Utils
32 import CLasH.Utils.Core.CoreTools
33 import CLasH.Utils.Pretty
34 import qualified CLasH.Normalize as Normalize
36 -----------------------------------------------------------------------------
37 -- Functions to generate VHDL for user-defined functions.
38 -----------------------------------------------------------------------------
40 -- | Create an entity for a given function
43 -> TranslatorSession Entity -- ^ The resulting entity
45 getEntity fname = Utils.makeCached fname tsEntities $ do
46 expr <- Normalize.getNormalized fname
47 -- Split the normalized expression
48 let (args, binds, res) = Normalize.splitNormalized expr
49 -- Generate ports for all non-empty types
50 args' <- catMaybesM $ mapM mkMap args
51 -- TODO: Handle Nothing
53 count <- getA tsEntityCounter
54 let vhdl_id = mkVHDLBasicId $ varToString fname ++ "Component_" ++ show count
55 putA tsEntityCounter (count + 1)
56 let ent_decl = createEntityAST vhdl_id args' res'
57 let signature = Entity vhdl_id args' res' ent_decl
61 --[(SignalId, SignalInfo)]
63 -> TranslatorSession (Maybe Port)
66 --info = Maybe.fromMaybe
67 -- (error $ "Signal not found in the name map? This should not happen!")
69 -- Assume the bndr has a valid VHDL id already
72 error_msg = "\nVHDL.createEntity.mkMap: Can not create entity: " ++ pprString fname ++ "\nbecause no type can be created for port: " ++ pprString bndr
74 type_mark_maybe <- MonadState.lift tsType $ vhdl_ty error_msg ty
75 case type_mark_maybe of
76 Just type_mark -> return $ Just (id, type_mark)
77 Nothing -> return Nothing
80 -- | Create the VHDL AST for an entity
82 AST.VHDLId -- ^ The name of the function
83 -> [Port] -- ^ The entity's arguments
84 -> Maybe Port -- ^ The entity's result
85 -> AST.EntityDec -- ^ The entity with the ent_decl filled in as well
87 createEntityAST vhdl_id args res =
88 AST.EntityDec vhdl_id ports
90 -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
91 ports = map (mkIfaceSigDec AST.In) args
92 ++ (Maybe.maybeToList res_port)
93 ++ [clk_port,resetn_port]
94 -- Add a clk port if we have state
95 clk_port = AST.IfaceSigDec clockId AST.In std_logicTM
96 resetn_port = AST.IfaceSigDec resetId AST.In std_logicTM
97 res_port = fmap (mkIfaceSigDec AST.Out) res
99 -- | Create a port declaration
101 AST.Mode -- ^ The mode for the port (In / Out)
102 -> Port -- ^ The id and type for the port
103 -> AST.IfaceSigDec -- ^ The resulting port declaration
105 mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
107 -- | Create an architecture for a given function
109 CoreSyn.CoreBndr -- ^ The function to get an architecture for
110 -> TranslatorSession (Architecture, [CoreSyn.CoreBndr])
111 -- ^ The architecture for this function
113 getArchitecture fname = Utils.makeCached fname tsArchitectures $ do
114 expr <- Normalize.getNormalized fname
115 -- Split the normalized expression
116 let (args, binds, res) = Normalize.splitNormalized expr
118 -- Get the entity for this function
119 signature <- getEntity fname
120 let entity_id = ent_id signature
122 -- Create signal declarations for all binders in the let expression, except
123 -- for the output port (that will already have an output port declared in
125 sig_dec_maybes <- mapM (mkSigDec . fst) (filter ((/=res).fst) binds)
126 let sig_decs = Maybe.catMaybes $ sig_dec_maybes
127 -- Process each bind, resulting in info about state variables and concurrent
129 (state_vars, sms) <- Monad.mapAndUnzipM dobind binds
130 let (in_state_maybes, out_state_maybes) = unzip state_vars
131 let (statementss, used_entitiess) = unzip sms
132 -- Create a state proc, if needed
133 state_proc <- case (Maybe.catMaybes in_state_maybes, Maybe.catMaybes out_state_maybes) of
134 ([in_state], [out_state]) -> mkStateProcSm (in_state, out_state)
135 ([], []) -> return []
136 (ins, outs) -> error $ "Weird use of state in " ++ show fname ++ ". In: " ++ show ins ++ " Out: " ++ show outs
137 -- Join the create statements and the (optional) state_proc
138 let statements = concat statementss ++ state_proc
139 -- Create the architecture
140 let arch = AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) statements
141 let used_entities = concat used_entitiess
142 return (arch, used_entities)
144 dobind :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The bind to process
145 -> TranslatorSession ((Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreBndr), ([AST.ConcSm], [CoreSyn.CoreBndr]))
146 -- ^ ((Input state variable, output state variable), (statements, used entities))
147 -- newtype unpacking is just a cast
148 dobind (bndr, unpacked@(CoreSyn.Cast packed coercion))
149 | hasStateType packed && not (hasStateType unpacked)
150 = return ((Just bndr, Nothing), ([], []))
151 -- With simplCore, newtype packing is just a cast
152 dobind (bndr, packed@(CoreSyn.Cast unpacked@(CoreSyn.Var state) coercion))
153 | hasStateType packed && not (hasStateType unpacked)
154 = return ((Nothing, Just state), ([], []))
155 -- Without simplCore, newtype packing uses a data constructor
156 dobind (bndr, (CoreSyn.App (CoreSyn.App (CoreSyn.Var con) (CoreSyn.Type _)) (CoreSyn.Var state)))
158 = return ((Nothing, Just state), ([], []))
159 -- Anything else is handled by mkConcSm
162 return ((Nothing, Nothing), sms)
165 (CoreSyn.CoreBndr, CoreSyn.CoreBndr) -- ^ The current and new state variables
166 -> TranslatorSession [AST.ConcSm] -- ^ The resulting statements
167 mkStateProcSm (old, new) = do
168 nonempty <- hasNonEmptyType old
170 then return [AST.CSPSm $ AST.ProcSm label [clockId,resetId] [statement]]
173 label = mkVHDLBasicId $ "state"
174 rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
175 wform = AST.Wform [AST.WformElem (AST.PrimName $ varToVHDLName new) Nothing]
176 clk_assign = AST.SigAssign (varToVHDLName old) wform
177 rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clockId)]
178 resetn_is_low = (AST.PrimName $ AST.NSimple resetId) AST.:=: (AST.PrimLit "'0'")
180 clk_statement = [AST.ElseIf rising_edge_clk [clk_assign]]
181 statement = AST.IfSm resetn_is_low reset_statement clk_statement Nothing
184 -- | Transforms a core binding into a VHDL concurrent statement
186 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
187 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
188 -- ^ The corresponding VHDL concurrent statements and entities
192 -- Ignore Cast expressions, they should not longer have any meaning as long as
193 -- the type works out. Throw away state repacking
194 mkConcSm (bndr, to@(CoreSyn.Cast from ty))
195 | hasStateType to && hasStateType from
197 mkConcSm (bndr, CoreSyn.Cast expr ty) = mkConcSm (bndr, expr)
199 -- Simple a = b assignments are just like applications, but without arguments.
200 -- We can't just generate an unconditional assignment here, since b might be a
201 -- top level binding (e.g., a function with no arguments).
202 mkConcSm (bndr, CoreSyn.Var v) = do
203 genApplication (Left bndr) v []
205 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
206 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
207 let valargs = get_val_args (Var.varType f) args
208 genApplication (Left bndr) f (map Left valargs)
210 -- A single alt case must be a selector. This means thee scrutinee is a simple
211 -- variable, the alternative is a dataalt with a single non-wild binder that
213 mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt]))
214 -- Don't generate VHDL for substate extraction
215 | hasStateType bndr = return ([], [])
218 (CoreSyn.DataAlt dc, bndrs, (CoreSyn.Var sel_bndr)) -> do
219 bndrs' <- Monad.filterM hasNonEmptyType bndrs
220 case List.elemIndex sel_bndr bndrs' of
222 labels <- MonadState.lift tsType $ getFieldLabels (Id.idType scrut)
223 let label = labels!!i
224 let sel_name = mkSelectedName (varToVHDLName scrut) label
225 let sel_expr = AST.PrimName sel_name
226 return ([mkUncondAssign (Left bndr) sel_expr], [])
227 Nothing -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case:\n" ++ (pprString expr)
229 _ -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case:\n" ++ (pprString expr)
231 -- Multiple case alt are be conditional assignments and have only wild
232 -- binders in the alts and only variables in the case values and a variable
233 -- for a scrutinee. We check the constructor of the second alt, since the
234 -- first is the default case, if there is any.
235 mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) b ty [(_, _, CoreSyn.Var false), (con, _, CoreSyn.Var true)])) = do
236 scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut
237 let cond_expr = scrut' AST.:=: (altconToVHDLExpr con)
238 true_expr <- MonadState.lift tsType $ varToVHDLExpr true
239 false_expr <- MonadState.lift tsType $ varToVHDLExpr false
240 return ([mkCondAssign (Left bndr) cond_expr true_expr false_expr], [])
242 mkConcSm (_, (CoreSyn.Case (CoreSyn.Var _) _ _ alts)) = error "\nVHDL.mkConcSm: Not in normal form: Case statement with more than two alternatives"
243 mkConcSm (_, CoreSyn.Case _ _ _ _) = error "\nVHDL.mkConcSm: Not in normal form: Case statement has does not have a simple variable as scrutinee"
244 mkConcSm (bndr, expr) = error $ "\nVHDL.mkConcSM: Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
246 -----------------------------------------------------------------------------
247 -- Functions to generate VHDL for builtin functions
248 -----------------------------------------------------------------------------
250 -- | A function to wrap a builder-like function that expects its arguments to
252 genExprArgs wrap dst func args = do
253 args' <- argsToVHDLExprs args
256 -- | Turn the all lefts into VHDL Expressions.
257 argsToVHDLExprs :: [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.Expr]
258 argsToVHDLExprs = catMaybesM . (mapM argToVHDLExpr)
260 argToVHDLExpr :: Either CoreSyn.CoreExpr AST.Expr -> TranslatorSession (Maybe AST.Expr)
261 argToVHDLExpr (Left expr) = MonadState.lift tsType $ do
262 let errmsg = "Generate.argToVHDLExpr: Using non-representable type? Should not happen!"
263 ty_maybe <- vhdl_ty errmsg expr
266 vhdl_expr <- varToVHDLExpr $ exprToVar expr
267 return $ Just vhdl_expr
268 Nothing -> return $ Nothing
270 argToVHDLExpr (Right expr) = return $ Just expr
272 -- A function to wrap a builder-like function that generates no component
275 (dst -> func -> args -> TranslatorSession [AST.ConcSm])
276 -> (dst -> func -> args -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr]))
277 genNoInsts wrap dst func args = do
278 concsms <- wrap dst func args
281 -- | A function to wrap a builder-like function that expects its arguments to
284 (dst -> func -> [Var.Var] -> res)
285 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
286 genVarArgs wrap dst func args = wrap dst func args'
288 args' = map exprToVar exprargs
289 -- Check (rather crudely) that all arguments are CoreExprs
290 (exprargs, []) = Either.partitionEithers args
292 -- | A function to wrap a builder-like function that expects its arguments to
295 (dst -> func -> [Literal.Literal] -> res)
296 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
297 genLitArgs wrap dst func args = wrap dst func args'
299 args' = map exprToLit litargs
300 -- FIXME: Check if we were passed an CoreSyn.App
301 litargs = concat (map getLiterals exprargs)
302 (exprargs, []) = Either.partitionEithers args
304 -- | A function to wrap a builder-like function that produces an expression
305 -- and expects it to be assigned to the destination.
307 ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession AST.Expr)
308 -> ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession [AST.ConcSm])
309 genExprRes wrap dst func args = do
310 expr <- wrap dst func args
311 return $ [mkUncondAssign dst expr]
313 -- | Generate a binary operator application. The first argument should be a
314 -- constructor from the AST.Expr type, e.g. AST.And.
315 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
316 genOperator2 op = genNoInsts $ genExprArgs $ genExprRes (genOperator2' op)
317 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
318 genOperator2' op _ f [arg1, arg2] = return $ op arg1 arg2
320 -- | Generate a unary operator application
321 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
322 genOperator1 op = genNoInsts $ genExprArgs $ genExprRes (genOperator1' op)
323 genOperator1' :: (AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
324 genOperator1' op _ f [arg] = return $ op arg
326 -- | Generate a unary operator application
327 genNegation :: BuiltinBuilder
328 genNegation = genNoInsts $ genVarArgs $ genExprRes genNegation'
329 genNegation' :: dst -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession AST.Expr
330 genNegation' _ f [arg] = do
331 arg1 <- MonadState.lift tsType $ varToVHDLExpr arg
332 let ty = Var.varType arg
333 let (tycon, args) = Type.splitTyConApp ty
334 let name = Name.getOccString (TyCon.tyConName tycon)
336 "SizedInt" -> return $ AST.Neg arg1
337 otherwise -> error $ "\nGenerate.genNegation': Negation allowed for type: " ++ show name
339 -- | Generate a function call from the destination binder, function name and a
340 -- list of expressions (its arguments)
341 genFCall :: Bool -> BuiltinBuilder
342 genFCall switch = genNoInsts $ genExprArgs $ genExprRes (genFCall' switch)
343 genFCall' :: Bool -> Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
344 genFCall' switch (Left res) f args = do
345 let fname = varToString f
346 let el_ty = if switch then (Var.varType res) else ((tfvec_elem . Var.varType) res)
347 id <- MonadState.lift tsType $ vectorFunId el_ty fname
348 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
349 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
350 genFCall' _ (Right name) _ _ = error $ "\nGenerate.genFCall': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
352 genFromSizedWord :: BuiltinBuilder
353 genFromSizedWord = genNoInsts $ genExprArgs genFromSizedWord'
354 genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm]
355 genFromSizedWord' (Left res) f args@[arg] = do
356 return $ [mkUncondAssign (Left res) arg]
357 -- let fname = varToString f
358 -- return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $
359 -- map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
360 genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
362 genResize :: BuiltinBuilder
363 genResize = genNoInsts $ genExprArgs $ genExprRes genResize'
364 genResize' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
365 genResize' (Left res) f [arg] = do {
366 ; let { ty = Var.varType res
367 ; (tycon, args) = Type.splitTyConApp ty
368 ; name = Name.getOccString (TyCon.tyConName tycon)
370 ; len <- case name of
371 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
372 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
373 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId resizeId))
374 [Nothing AST.:=>: AST.ADExpr arg, Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
376 genResize' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
378 -- FIXME: I'm calling genLitArgs which is very specific function,
379 -- which needs to be fixed as well
380 genFromInteger :: BuiltinBuilder
381 genFromInteger = genNoInsts $ genLitArgs $ genExprRes genFromInteger'
382 genFromInteger' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [Literal.Literal] -> TranslatorSession AST.Expr
383 genFromInteger' (Left res) f lits = do {
384 ; let { ty = Var.varType res
385 ; (tycon, args) = Type.splitTyConApp ty
386 ; name = Name.getOccString (TyCon.tyConName tycon)
388 ; len <- case name of
389 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
390 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
392 ; bound <- MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty)
393 ; return $ floor (logBase 2 (fromInteger (toInteger (bound)))) + 1
395 ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId ; "RangedWord" -> toUnsignedId
396 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname))
397 [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
401 genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
403 genSizedInt :: BuiltinBuilder
404 genSizedInt = genFromInteger
407 -- | Generate a Builder for the builtin datacon TFVec
408 genTFVec :: BuiltinBuilder
409 genTFVec (Left res) f [Left (CoreSyn.Let (CoreSyn.Rec letBinders) letRes)] = do {
410 -- Generate Assignments for all the binders
411 ; letAssigns <- mapM genBinderAssign letBinders
412 -- Generate assignments for the result (which might be another let binding)
413 ; (resBinders,resAssignments) <- genResAssign letRes
414 -- Get all the Assigned binders
415 ; let assignedBinders = Maybe.catMaybes (map fst letAssigns)
416 -- Make signal names for all the assigned binders
417 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) (assignedBinders ++ resBinders)
418 -- Assign all the signals to the resulting vector
419 ; let { vecsigns = mkAggregateSignal sigs
420 ; vecassign = mkUncondAssign (Left res) vecsigns
422 -- Generate all the signal declaration for the assigned binders
423 ; sig_dec_maybes <- mapM mkSigDec (assignedBinders ++ resBinders)
424 ; let { sig_decs = map (AST.BDISD) (Maybe.catMaybes $ sig_dec_maybes)
425 -- Setup the VHDL Block
426 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
427 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) sig_decs ((concat (map snd letAssigns)) ++ resAssignments ++ [vecassign])
429 -- Return the block statement coressponding to the TFVec literal
430 ; return $ [AST.CSBSm block]
433 genBinderAssign :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -> TranslatorSession (Maybe CoreSyn.CoreBndr, [AST.ConcSm])
434 -- For now we only translate applications
435 genBinderAssign (bndr, app@(CoreSyn.App _ _)) = do
436 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
437 let valargs = get_val_args (Var.varType f) args
438 apps <- genApplication (Left bndr) f (map Left valargs)
439 return (Just bndr, apps)
440 genBinderAssign _ = return (Nothing,[])
441 genResAssign :: CoreSyn.CoreExpr -> TranslatorSession ([CoreSyn.CoreBndr], [AST.ConcSm])
442 genResAssign app@(CoreSyn.App _ letexpr) = do
444 (CoreSyn.Let (CoreSyn.Rec letbndrs) letres) -> do
445 letapps <- mapM genBinderAssign letbndrs
446 let bndrs = Maybe.catMaybes (map fst letapps)
447 let app = (map snd letapps)
448 (vars, apps) <- genResAssign letres
449 return ((bndrs ++ vars),((concat app) ++ apps))
450 otherwise -> return ([],[])
451 genResAssign _ = return ([],[])
453 genTFVec (Left res) f [Left app@(CoreSyn.App _ _)] = do {
454 ; let { elems = reduceCoreListToHsList app
455 -- Make signal names for all the binders
456 ; binders = map (\expr -> case expr of
458 otherwise -> error $ "\nGenerate.genTFVec: Cannot generate TFVec: "
459 ++ show res ++ ", with elems:\n" ++ show elems ++ "\n" ++ pprString elems) elems
461 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) binders
462 -- Assign all the signals to the resulting vector
463 ; let { vecsigns = mkAggregateSignal sigs
464 ; vecassign = mkUncondAssign (Left res) vecsigns
465 -- Setup the VHDL Block
466 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
467 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) [] [vecassign]
469 -- Return the block statement coressponding to the TFVec literal
470 ; return $ [AST.CSBSm block]
473 genTFVec (Left name) _ [Left xs] = error $ "\nGenerate.genTFVec: Cannot generate TFVec: " ++ show name ++ ", with elems:\n" ++ show xs ++ "\n" ++ pprString xs
475 genTFVec (Right name) _ _ = error $ "\nGenerate.genTFVec: Cannot generate TFVec assigned to VHDLName: " ++ show name
477 -- | Generate a generate statement for the builtin function "map"
478 genMap :: BuiltinBuilder
479 genMap (Left res) f [Left mapped_f, Left (CoreSyn.Var arg)] = do {
480 -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL
481 -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since
482 -- we must index it (which we couldn't if it was a VHDL Expr, since only
483 -- VHDLNames can be indexed).
484 -- Setup the generate scheme
485 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
486 -- TODO: Use something better than varToString
487 ; let { label = mkVHDLExtId ("mapVector" ++ (varToString res))
488 ; n_id = mkVHDLBasicId "n"
489 ; n_expr = idToVHDLExpr n_id
490 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
491 ; genScheme = AST.ForGn n_id range
492 -- Create the content of the generate statement: Applying the mapped_f to
493 -- each of the elements in arg, storing to each element in res
494 ; resname = mkIndexedName (varToVHDLName res) n_expr
495 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
496 ; (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f
497 ; valargs = get_val_args (Var.varType real_f) already_mapped_args
499 ; (app_concsms, used) <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr])
500 -- Return the generate statement
501 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
504 genMap' (Right name) _ _ = error $ "\nGenerate.genMap': Cannot generate map function call assigned to a VHDLName: " ++ show name
506 genZipWith :: BuiltinBuilder
507 genZipWith = genVarArgs genZipWith'
508 genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
509 genZipWith' (Left res) f args@[zipped_f, arg1, arg2] = do {
510 -- Setup the generate scheme
511 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
512 -- TODO: Use something better than varToString
513 ; let { label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
514 ; n_id = mkVHDLBasicId "n"
515 ; n_expr = idToVHDLExpr n_id
516 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
517 ; genScheme = AST.ForGn n_id range
518 -- Create the content of the generate statement: Applying the zipped_f to
519 -- each of the elements in arg1 and arg2, storing to each element in res
520 ; resname = mkIndexedName (varToVHDLName res) n_expr
521 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
522 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
524 ; (app_concsms, used) <- genApplication (Right resname) zipped_f [Right argexpr1, Right argexpr2]
525 -- Return the generate functions
526 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
529 genFoldl :: BuiltinBuilder
530 genFoldl = genFold True
532 genFoldr :: BuiltinBuilder
533 genFoldr = genFold False
535 genFold :: Bool -> BuiltinBuilder
536 genFold left = genVarArgs (genFold' left)
538 genFold' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
539 genFold' left res f args@[folded_f , start ,vec]= do
540 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty (Var.varType vec))
541 genFold'' len left res f args
543 genFold'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
544 -- Special case for an empty input vector, just assign start to res
545 genFold'' len left (Left res) _ [_, start, vec] | len == 0 = do
546 arg <- MonadState.lift tsType $ varToVHDLExpr start
547 return ([mkUncondAssign (Left res) arg], [])
549 genFold'' len left (Left res) f [folded_f, start, vec] = do
551 --len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
552 -- An expression for len-1
553 let len_min_expr = (AST.PrimLit $ show (len-1))
554 -- evec is (TFVec n), so it still needs an element type
555 let (nvec, _) = Type.splitAppTy (Var.varType vec)
556 -- Put the type of the start value in nvec, this will be the type of our
558 let tmp_ty = Type.mkAppTy nvec (Var.varType start)
559 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
560 -- TODO: Handle Nothing
561 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdl_ty error_msg tmp_ty
562 -- Setup the generate scheme
563 let gen_label = mkVHDLExtId ("foldlVector" ++ (varToString vec))
564 let block_label = mkVHDLExtId ("foldlVector" ++ (varToString res))
565 let gen_range = if left then AST.ToRange (AST.PrimLit "0") len_min_expr
566 else AST.DownRange len_min_expr (AST.PrimLit "0")
567 let gen_scheme = AST.ForGn n_id gen_range
568 -- Make the intermediate vector
569 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
570 -- Create the generate statement
571 cells' <- sequence [genFirstCell, genOtherCell]
572 let (cells, useds) = unzip cells'
573 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
574 -- Assign tmp[len-1] or tmp[0] to res
575 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr (if left then
576 (mkIndexedName tmp_name (AST.PrimLit $ show (len-1))) else
577 (mkIndexedName tmp_name (AST.PrimLit "0")))
578 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
579 return ([AST.CSBSm block], concat useds)
581 -- An id for the counter
582 n_id = mkVHDLBasicId "n"
583 n_cur = idToVHDLExpr n_id
584 -- An expression for previous n
585 n_prev = if left then (n_cur AST.:-: (AST.PrimLit "1"))
586 else (n_cur AST.:+: (AST.PrimLit "1"))
587 -- An id for the tmp result vector
588 tmp_id = mkVHDLBasicId "tmp"
589 tmp_name = AST.NSimple tmp_id
590 -- Generate parts of the fold
591 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
593 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
594 let cond_label = mkVHDLExtId "firstcell"
595 -- if n == 0 or n == len-1
596 let cond_scheme = AST.IfGn $ n_cur AST.:=: (if left then (AST.PrimLit "0")
597 else (AST.PrimLit $ show (len-1)))
598 -- Output to tmp[current n]
599 let resname = mkIndexedName tmp_name n_cur
601 argexpr1 <- MonadState.lift tsType $ varToVHDLExpr start
602 -- Input from vec[current n]
603 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
604 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
605 [Right argexpr1, Right argexpr2]
607 [Right argexpr2, Right argexpr1]
609 -- Return the conditional generate part
610 return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
613 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
614 let cond_label = mkVHDLExtId "othercell"
615 -- if n > 0 or n < len-1
616 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (if left then (AST.PrimLit "0")
617 else (AST.PrimLit $ show (len-1)))
618 -- Output to tmp[current n]
619 let resname = mkIndexedName tmp_name n_cur
620 -- Input from tmp[previous n]
621 let argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
622 -- Input from vec[current n]
623 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
624 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
625 [Right argexpr1, Right argexpr2]
627 [Right argexpr2, Right argexpr1]
629 -- Return the conditional generate part
630 return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
632 -- | Generate a generate statement for the builtin function "zip"
633 genZip :: BuiltinBuilder
634 genZip = genNoInsts $ genVarArgs genZip'
635 genZip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
636 genZip' (Left res) f args@[arg1, arg2] = do {
637 -- Setup the generate scheme
638 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
639 -- TODO: Use something better than varToString
640 ; let { label = mkVHDLExtId ("zipVector" ++ (varToString res))
641 ; n_id = mkVHDLBasicId "n"
642 ; n_expr = idToVHDLExpr n_id
643 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
644 ; genScheme = AST.ForGn n_id range
645 ; resname' = mkIndexedName (varToVHDLName res) n_expr
646 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
647 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
649 ; labels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType res))
650 ; let { resnameA = mkSelectedName resname' (labels!!0)
651 ; resnameB = mkSelectedName resname' (labels!!1)
652 ; resA_assign = mkUncondAssign (Right resnameA) argexpr1
653 ; resB_assign = mkUncondAssign (Right resnameB) argexpr2
655 -- Return the generate functions
656 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
659 -- | Generate a generate statement for the builtin function "fst"
660 genFst :: BuiltinBuilder
661 genFst = genNoInsts $ genVarArgs genFst'
662 genFst' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
663 genFst' (Left res) f args@[arg] = do {
664 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg)
665 ; let { argexpr' = varToVHDLName arg
666 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!0)
667 ; assign = mkUncondAssign (Left res) argexprA
669 -- Return the generate functions
673 -- | Generate a generate statement for the builtin function "snd"
674 genSnd :: BuiltinBuilder
675 genSnd = genNoInsts $ genVarArgs genSnd'
676 genSnd' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
677 genSnd' (Left res) f args@[arg] = do {
678 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg)
679 ; let { argexpr' = varToVHDLName arg
680 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!1)
681 ; assign = mkUncondAssign (Left res) argexprB
683 -- Return the generate functions
687 -- | Generate a generate statement for the builtin function "unzip"
688 genUnzip :: BuiltinBuilder
689 genUnzip = genNoInsts $ genVarArgs genUnzip'
690 genUnzip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
691 genUnzip' (Left res) f args@[arg] = do {
692 -- Setup the generate scheme
693 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
694 -- TODO: Use something better than varToString
695 ; let { label = mkVHDLExtId ("unzipVector" ++ (varToString res))
696 ; n_id = mkVHDLBasicId "n"
697 ; n_expr = idToVHDLExpr n_id
698 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
699 ; genScheme = AST.ForGn n_id range
700 ; resname' = varToVHDLName res
701 ; argexpr' = mkIndexedName (varToVHDLName arg) n_expr
703 ; reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
704 ; arglabels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType arg))
705 ; let { resnameA = mkIndexedName (mkSelectedName resname' (reslabels!!0)) n_expr
706 ; resnameB = mkIndexedName (mkSelectedName resname' (reslabels!!1)) n_expr
707 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!0)
708 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!1)
709 ; resA_assign = mkUncondAssign (Right resnameA) argexprA
710 ; resB_assign = mkUncondAssign (Right resnameB) argexprB
712 -- Return the generate functions
713 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
716 genCopy :: BuiltinBuilder
717 genCopy = genNoInsts $ genVarArgs genCopy'
718 genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
719 genCopy' (Left res) f args@[arg] =
721 resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others)
722 (AST.PrimName $ (varToVHDLName arg))]
723 out_assign = mkUncondAssign (Left res) resExpr
727 genConcat :: BuiltinBuilder
728 genConcat = genNoInsts $ genVarArgs genConcat'
729 genConcat' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
730 genConcat' (Left res) f args@[arg] = do {
731 -- Setup the generate scheme
732 ; len1 <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
733 ; let (_, nvec) = Type.splitAppTy (Var.varType arg)
734 ; len2 <- MonadState.lift tsType $ tfp_to_int $ tfvec_len_ty nvec
735 -- TODO: Use something better than varToString
736 ; let { label = mkVHDLExtId ("concatVector" ++ (varToString res))
737 ; n_id = mkVHDLBasicId "n"
738 ; n_expr = idToVHDLExpr n_id
739 ; fromRange = n_expr AST.:*: (AST.PrimLit $ show len2)
740 ; genScheme = AST.ForGn n_id range
741 -- Create the content of the generate statement: Applying the mapped_f to
742 -- each of the elements in arg, storing to each element in res
743 ; toRange = (n_expr AST.:*: (AST.PrimLit $ show len2)) AST.:+: (AST.PrimLit $ show (len2-1))
744 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len1-1))
745 ; resname = vecSlice fromRange toRange
746 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
747 ; out_assign = mkUncondAssign (Right resname) argexpr
749 -- Return the generate statement
750 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [out_assign]]
753 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
754 (AST.ToRange init last))
756 genIteraten :: BuiltinBuilder
757 genIteraten dst f args = genIterate dst f (tail args)
759 genIterate :: BuiltinBuilder
760 genIterate = genIterateOrGenerate True
762 genGeneraten :: BuiltinBuilder
763 genGeneraten dst f args = genGenerate dst f (tail args)
765 genGenerate :: BuiltinBuilder
766 genGenerate = genIterateOrGenerate False
768 genIterateOrGenerate :: Bool -> BuiltinBuilder
769 genIterateOrGenerate iter = genVarArgs (genIterateOrGenerate' iter)
771 genIterateOrGenerate' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
772 genIterateOrGenerate' iter (Left res) f args = do
773 len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
774 genIterateOrGenerate'' len iter (Left res) f args
776 genIterateOrGenerate'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
777 -- Special case for an empty input vector, just assign start to res
778 genIterateOrGenerate'' len iter (Left res) _ [app_f, start] | len == 0 = return ([mkUncondAssign (Left res) (AST.PrimLit "\"\"")], [])
780 genIterateOrGenerate'' len iter (Left res) f [app_f, start] = do
782 -- len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
783 -- An expression for len-1
784 let len_min_expr = (AST.PrimLit $ show (len-1))
785 -- -- evec is (TFVec n), so it still needs an element type
786 -- let (nvec, _) = splitAppTy (Var.varType vec)
787 -- -- Put the type of the start value in nvec, this will be the type of our
788 -- -- temporary vector
789 let tmp_ty = Var.varType res
790 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
791 -- TODO: Handle Nothing
792 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdl_ty error_msg tmp_ty
793 -- Setup the generate scheme
794 let gen_label = mkVHDLExtId ("iterateVector" ++ (varToString start))
795 let block_label = mkVHDLExtId ("iterateVector" ++ (varToString res))
796 let gen_range = AST.ToRange (AST.PrimLit "0") len_min_expr
797 let gen_scheme = AST.ForGn n_id gen_range
798 -- Make the intermediate vector
799 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
800 -- Create the generate statement
801 cells' <- sequence [genFirstCell, genOtherCell]
802 let (cells, useds) = unzip cells'
803 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
804 -- Assign tmp[len-1] or tmp[0] to res
805 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr tmp_name
806 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
807 return ([AST.CSBSm block], concat useds)
809 -- An id for the counter
810 n_id = mkVHDLBasicId "n"
811 n_cur = idToVHDLExpr n_id
812 -- An expression for previous n
813 n_prev = n_cur AST.:-: (AST.PrimLit "1")
814 -- An id for the tmp result vector
815 tmp_id = mkVHDLBasicId "tmp"
816 tmp_name = AST.NSimple tmp_id
817 -- Generate parts of the fold
818 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
820 let cond_label = mkVHDLExtId "firstcell"
821 -- if n == 0 or n == len-1
822 let cond_scheme = AST.IfGn $ n_cur AST.:=: (AST.PrimLit "0")
823 -- Output to tmp[current n]
824 let resname = mkIndexedName tmp_name n_cur
826 argexpr <- MonadState.lift tsType $ varToVHDLExpr start
827 let startassign = mkUncondAssign (Right resname) argexpr
828 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
829 -- Return the conditional generate part
830 let gensm = AST.GenerateSm cond_label cond_scheme [] (if iter then
838 let cond_label = mkVHDLExtId "othercell"
839 -- if n > 0 or n < len-1
840 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (AST.PrimLit "0")
841 -- Output to tmp[current n]
842 let resname = mkIndexedName tmp_name n_cur
843 -- Input from tmp[previous n]
844 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
845 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
846 -- Return the conditional generate part
847 return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
849 genBlockRAM :: BuiltinBuilder
850 genBlockRAM = genNoInsts $ genExprArgs genBlockRAM'
852 genBlockRAM' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm]
853 genBlockRAM' (Left res) f args@[data_in,rdaddr,wraddr,wrenable] = do
855 let (tup,data_out) = Type.splitAppTy (Var.varType res)
856 let (tup',ramvec) = Type.splitAppTy tup
857 let Just realram = Type.coreView ramvec
858 let Just (tycon, types) = Type.splitTyConApp_maybe realram
859 Just ram_vhdl_ty <- MonadState.lift tsType $ vhdl_ty "wtf" (head types)
860 -- Make the intermediate vector
861 let ram_dec = AST.BDISD $ AST.SigDec ram_id ram_vhdl_ty Nothing
862 -- Get the data_out name
863 reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
864 let resname' = varToVHDLName res
865 let resname = mkSelectedName resname' (reslabels!!0)
866 let rdaddr_int = genExprFCall (mkVHDLBasicId toIntegerId) rdaddr
867 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName (AST.NSimple ram_id) rdaddr_int
868 let assign = mkUncondAssign (Right resname) argexpr
869 let block_label = mkVHDLExtId ("blockRAM" ++ (varToString res))
870 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [ram_dec] [assign, mkUpdateProcSm]
871 return [AST.CSBSm block]
873 ram_id = mkVHDLBasicId "ram"
874 mkUpdateProcSm :: AST.ConcSm
875 mkUpdateProcSm = AST.CSPSm $ AST.ProcSm proclabel [clockId] [statement]
877 proclabel = mkVHDLBasicId "updateRAM"
878 rising_edge = mkVHDLBasicId "rising_edge"
879 wraddr_int = genExprFCall (mkVHDLBasicId toIntegerId) wraddr
880 ramloc = mkIndexedName (AST.NSimple ram_id) wraddr_int
881 wform = AST.Wform [AST.WformElem data_in Nothing]
882 ramassign = AST.SigAssign ramloc wform
883 rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
884 statement = AST.IfSm (AST.And rising_edge_clk wrenable) [ramassign] [] Nothing
886 -----------------------------------------------------------------------------
887 -- Function to generate VHDL for applications
888 -----------------------------------------------------------------------------
890 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
891 -> CoreSyn.CoreBndr -- ^ The function to apply
892 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
893 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
894 -- ^ The corresponding VHDL concurrent statements and entities
896 genApplication dst f args = do
897 case Var.isGlobalId f of
899 top <- isTopLevelBinder f
902 -- Local binder that references a top level binding. Generate a
903 -- component instantiation.
904 signature <- getEntity f
905 args' <- argsToVHDLExprs args
906 let entity_id = ent_id signature
907 -- TODO: Using show here isn't really pretty, but we'll need some
908 -- unique-ish value...
909 let label = "comp_ins_" ++ (either (prettyShow . varToVHDLName) prettyShow) dst
910 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
911 return ([mkComponentInst label entity_id portmaps], [f])
913 -- Not a top level binder, so this must be a local variable reference.
914 -- It should have a representable type (and thus, no arguments) and a
915 -- signal should be generated for it. Just generate an unconditional
917 f' <- MonadState.lift tsType $ varToVHDLExpr f
918 return $ ([mkUncondAssign dst f'], [])
920 case Var.idDetails f of
921 IdInfo.DataConWorkId dc -> case dst of
922 -- It's a datacon. Create a record from its arguments.
924 -- We have the bndr, so we can get at the type
925 labels <- MonadState.lift tsType $ getFieldLabels (Var.varType bndr)
926 args' <- argsToVHDLExprs args
927 return $ (zipWith mkassign labels $ args', [])
929 mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
931 let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
932 mkUncondAssign (Right sel_name) arg
933 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconstructor application without an original binder"
934 IdInfo.DataConWrapId dc -> case dst of
935 -- It's a datacon. Create a record from its arguments.
937 case (Map.lookup (varToString f) globalNameTable) of
938 Just (arg_count, builder) ->
939 if length args == arg_count then
942 error $ "\nGenerate.genApplication(DataConWrapId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
943 Nothing -> error $ "\nGenerate.genApplication: Can't generate dataconwrapper: " ++ (show dc)
944 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconwrapper application without an original binder"
945 IdInfo.VanillaId -> do
946 -- It's a global value imported from elsewhere. These can be builtin
947 -- functions. Look up the function name in the name table and execute
948 -- the associated builder if there is any and the argument count matches
949 -- (this should always be the case if it typechecks, but just to be
951 case (Map.lookup (varToString f) globalNameTable) of
952 Just (arg_count, builder) ->
953 if length args == arg_count then
956 error $ "\nGenerate.genApplication(VanillaId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
958 top <- isTopLevelBinder f
961 -- Local binder that references a top level binding. Generate a
962 -- component instantiation.
963 signature <- getEntity f
964 args' <- argsToVHDLExprs args
965 let entity_id = ent_id signature
966 -- TODO: Using show here isn't really pretty, but we'll need some
967 -- unique-ish value...
968 let label = "comp_ins_" ++ (either show prettyShow) dst
969 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
970 return ([mkComponentInst label entity_id portmaps], [f])
972 -- Not a top level binder, so this must be a local variable reference.
973 -- It should have a representable type (and thus, no arguments) and a
974 -- signal should be generated for it. Just generate an unconditional
976 -- FIXME : I DONT KNOW IF THE ABOVE COMMENT HOLDS HERE, SO FOR NOW JUST ERROR!
977 -- f' <- MonadState.lift tsType $ varToVHDLExpr f
978 -- return $ ([mkUncondAssign dst f'], [])
979 error $ ("\nGenerate.genApplication(VanillaId): Using function from another module that is not a known builtin: " ++ (pprString f))
980 IdInfo.ClassOpId cls -> do
981 -- FIXME: Not looking for what instance this class op is called for
982 -- Is quite stupid of course.
983 case (Map.lookup (varToString f) globalNameTable) of
984 Just (arg_count, builder) ->
985 if length args == arg_count then
988 error $ "\nGenerate.genApplication(ClassOpId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
989 Nothing -> error $ "\nGenerate.genApplication(ClassOpId): Using function from another module that is not a known builtin: " ++ pprString f
990 details -> error $ "\nGenerate.genApplication: Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
992 -----------------------------------------------------------------------------
993 -- Functions to generate functions dealing with vectors.
994 -----------------------------------------------------------------------------
996 -- Returns the VHDLId of the vector function with the given name for the given
997 -- element type. Generates -- this function if needed.
998 vectorFunId :: Type.Type -> String -> TypeSession AST.VHDLId
999 vectorFunId el_ty fname = do
1000 let error_msg = "\nGenerate.vectorFunId: Can not construct vector function for element: " ++ pprString el_ty
1001 -- TODO: Handle the Nothing case?
1002 Just elemTM <- vhdl_ty error_msg el_ty
1003 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
1004 -- the VHDLState or something.
1005 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
1006 typefuns <- getA tsTypeFuns
1007 case Map.lookup (OrdType el_ty, fname) typefuns of
1008 -- Function already generated, just return it
1009 Just (id, _) -> return id
1010 -- Function not generated yet, generate it
1012 let functions = genUnconsVectorFuns elemTM vectorTM
1013 case lookup fname functions of
1015 modA tsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, (fst body))
1016 mapM_ (vectorFunId el_ty) (snd body)
1018 Nothing -> error $ "\nGenerate.vectorFunId: I don't know how to generate vector function " ++ fname
1020 function_id = mkVHDLExtId fname
1022 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
1023 -> AST.TypeMark -- ^ type of the vector
1024 -> [(String, (AST.SubProgBody, [String]))]
1025 genUnconsVectorFuns elemTM vectorTM =
1026 [ (exId, (AST.SubProgBody exSpec [] [exExpr],[]))
1027 , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr1,replaceExpr2,replaceRet],[]))
1028 , (lastId, (AST.SubProgBody lastSpec [] [lastExpr],[]))
1029 , (initId, (AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet],[]))
1030 , (minimumId, (AST.SubProgBody minimumSpec [] [minimumExpr],[]))
1031 , (takeId, (AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet],[minimumId]))
1032 , (dropId, (AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet],[]))
1033 , (plusgtId, (AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet],[]))
1034 , (emptyId, (AST.SubProgBody emptySpec [AST.SPVD emptyVar] [emptyExpr],[]))
1035 , (singletonId, (AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet],[]))
1036 , (copynId, (AST.SubProgBody copynSpec [AST.SPVD copynVar] [copynExpr],[]))
1037 , (selId, (AST.SubProgBody selSpec [AST.SPVD selVar] [selFor, selRet],[]))
1038 , (ltplusId, (AST.SubProgBody ltplusSpec [AST.SPVD ltplusVar] [ltplusExpr, ltplusRet],[]))
1039 , (plusplusId, (AST.SubProgBody plusplusSpec [AST.SPVD plusplusVar] [plusplusExpr, plusplusRet],[]))
1040 , (lengthTId, (AST.SubProgBody lengthTSpec [] [lengthTExpr],[]))
1041 , (shiftlId, (AST.SubProgBody shiftlSpec [AST.SPVD shiftlVar] [shiftlExpr, shiftlRet], [initId]))
1042 , (shiftrId, (AST.SubProgBody shiftrSpec [AST.SPVD shiftrVar] [shiftrExpr, shiftrRet], [tailId]))
1043 , (nullId, (AST.SubProgBody nullSpec [] [nullExpr], []))
1044 , (rotlId, (AST.SubProgBody rotlSpec [AST.SPVD rotlVar] [rotlExpr, rotlRet], [nullId, lastId, initId]))
1045 , (rotrId, (AST.SubProgBody rotrSpec [AST.SPVD rotrVar] [rotrExpr, rotrRet], [nullId, tailId, headId]))
1046 , (reverseId, (AST.SubProgBody reverseSpec [AST.SPVD reverseVar] [reverseFor, reverseRet], []))
1049 ixPar = AST.unsafeVHDLBasicId "ix"
1050 vecPar = AST.unsafeVHDLBasicId "vec"
1051 vec1Par = AST.unsafeVHDLBasicId "vec1"
1052 vec2Par = AST.unsafeVHDLBasicId "vec2"
1053 nPar = AST.unsafeVHDLBasicId "n"
1054 leftPar = AST.unsafeVHDLBasicId "nLeft"
1055 rightPar = AST.unsafeVHDLBasicId "nRight"
1056 iId = AST.unsafeVHDLBasicId "i"
1058 aPar = AST.unsafeVHDLBasicId "a"
1059 fPar = AST.unsafeVHDLBasicId "f"
1060 sPar = AST.unsafeVHDLBasicId "s"
1061 resId = AST.unsafeVHDLBasicId "res"
1062 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
1063 AST.IfaceVarDec ixPar unsignedTM] elemTM
1064 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
1065 (AST.IndexedName (AST.NSimple vecPar) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple $ ixPar)]))
1066 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
1067 , AST.IfaceVarDec iPar unsignedTM
1068 , AST.IfaceVarDec aPar elemTM
1070 -- variable res : fsvec_x (0 to vec'length-1);
1073 (AST.SubtypeIn vectorTM
1074 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1075 [AST.ToRange (AST.PrimLit "0")
1076 (AST.PrimName (AST.NAttribute $
1077 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1078 (AST.PrimLit "1")) ]))
1080 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
1081 replaceExpr1 = AST.NSimple resId AST.:= AST.PrimName (AST.NSimple vecPar)
1082 replaceExpr2 = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple $ iPar)]) AST.:= AST.PrimName (AST.NSimple aPar)
1083 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1084 vecSlice init last = AST.PrimName (AST.NSlice
1086 (AST.NSimple vecPar)
1087 (AST.ToRange init last)))
1088 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
1089 -- return vec(vec'length-1);
1090 lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
1091 (AST.NSimple vecPar)
1092 [AST.PrimName (AST.NAttribute $
1093 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1094 AST.:-: AST.PrimLit "1"])))
1095 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1096 -- variable res : fsvec_x (0 to vec'length-2);
1099 (AST.SubtypeIn vectorTM
1100 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1101 [AST.ToRange (AST.PrimLit "0")
1102 (AST.PrimName (AST.NAttribute $
1103 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1104 (AST.PrimLit "2")) ]))
1106 -- resAST.:= vec(0 to vec'length-2)
1107 initExpr = AST.NSimple resId AST.:= (vecSlice
1109 (AST.PrimName (AST.NAttribute $
1110 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1111 AST.:-: AST.PrimLit "2"))
1112 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1113 minimumSpec = AST.Function (mkVHDLExtId minimumId) [AST.IfaceVarDec leftPar naturalTM,
1114 AST.IfaceVarDec rightPar naturalTM ] naturalTM
1115 minimumExpr = AST.IfSm ((AST.PrimName $ AST.NSimple leftPar) AST.:<: (AST.PrimName $ AST.NSimple rightPar))
1116 [AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple leftPar)]
1118 (Just $ AST.Else [minimumExprRet])
1119 where minimumExprRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple rightPar)
1120 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
1121 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1122 -- variable res : fsvec_x (0 to (minimum (n,vec'length))-1);
1123 minLength = AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId minimumId))
1124 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple nPar)
1125 ,Nothing AST.:=>: AST.ADExpr (AST.PrimName (AST.NAttribute $
1126 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]
1129 (AST.SubtypeIn vectorTM
1130 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1131 [AST.ToRange (AST.PrimLit "0")
1133 (AST.PrimLit "1")) ]))
1135 -- res AST.:= vec(0 to n-1)
1136 takeExpr = AST.NSimple resId AST.:=
1137 (vecSlice (AST.PrimLit "0")
1138 (minLength AST.:-: AST.PrimLit "1"))
1139 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1140 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
1141 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1142 -- variable res : fsvec_x (0 to vec'length-n-1);
1145 (AST.SubtypeIn vectorTM
1146 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1147 [AST.ToRange (AST.PrimLit "0")
1148 (AST.PrimName (AST.NAttribute $
1149 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1150 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
1152 -- res AST.:= vec(n to vec'length-1)
1153 dropExpr = AST.NSimple resId AST.:= (vecSlice
1154 (AST.PrimName $ AST.NSimple nPar)
1155 (AST.PrimName (AST.NAttribute $
1156 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1157 AST.:-: AST.PrimLit "1"))
1158 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1159 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
1160 AST.IfaceVarDec vecPar vectorTM] vectorTM
1161 -- variable res : fsvec_x (0 to vec'length);
1164 (AST.SubtypeIn vectorTM
1165 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1166 [AST.ToRange (AST.PrimLit "0")
1167 (AST.PrimName (AST.NAttribute $
1168 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1170 plusgtExpr = AST.NSimple resId AST.:=
1171 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
1172 (AST.PrimName $ AST.NSimple vecPar))
1173 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1174 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
1177 (AST.SubtypeIn vectorTM
1178 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1179 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "-1")]))
1181 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1182 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
1184 -- variable res : fsvec_x (0 to 0) := (others => a);
1187 (AST.SubtypeIn vectorTM
1188 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1189 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
1190 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1191 (AST.PrimName $ AST.NSimple aPar)])
1192 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1193 copynSpec = AST.Function (mkVHDLExtId copynId) [AST.IfaceVarDec nPar naturalTM,
1194 AST.IfaceVarDec aPar elemTM ] vectorTM
1195 -- variable res : fsvec_x (0 to n-1) := (others => a);
1198 (AST.SubtypeIn vectorTM
1199 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1200 [AST.ToRange (AST.PrimLit "0")
1201 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1202 (AST.PrimLit "1")) ]))
1203 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1204 (AST.PrimName $ AST.NSimple aPar)])
1206 copynExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1207 selSpec = AST.Function (mkVHDLExtId selId) [AST.IfaceVarDec fPar naturalTM,
1208 AST.IfaceVarDec sPar naturalTM,
1209 AST.IfaceVarDec nPar naturalTM,
1210 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1211 -- variable res : fsvec_x (0 to n-1);
1214 (AST.SubtypeIn vectorTM
1215 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1216 [AST.ToRange (AST.PrimLit "0")
1217 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1218 (AST.PrimLit "1")) ])
1221 -- for i res'range loop
1222 -- res(i) := vec(f+i*s);
1224 selFor = AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple $ rangeId) Nothing) [selAssign]
1225 -- res(i) := vec(f+i*s);
1226 selAssign = let origExp = AST.PrimName (AST.NSimple fPar) AST.:+:
1227 (AST.PrimName (AST.NSimple iId) AST.:*:
1228 AST.PrimName (AST.NSimple sPar)) in
1229 AST.NIndexed (AST.IndexedName (AST.NSimple resId) [AST.PrimName (AST.NSimple iId)]) AST.:=
1230 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [origExp]))
1232 selRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1233 ltplusSpec = AST.Function (mkVHDLExtId ltplusId) [AST.IfaceVarDec vecPar vectorTM,
1234 AST.IfaceVarDec aPar elemTM] vectorTM
1235 -- variable res : fsvec_x (0 to vec'length);
1238 (AST.SubtypeIn vectorTM
1239 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1240 [AST.ToRange (AST.PrimLit "0")
1241 (AST.PrimName (AST.NAttribute $
1242 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1244 ltplusExpr = AST.NSimple resId AST.:=
1245 ((AST.PrimName $ AST.NSimple vecPar) AST.:&:
1246 (AST.PrimName $ AST.NSimple aPar))
1247 ltplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1248 plusplusSpec = AST.Function (mkVHDLExtId plusplusId) [AST.IfaceVarDec vec1Par vectorTM,
1249 AST.IfaceVarDec vec2Par vectorTM]
1251 -- variable res : fsvec_x (0 to vec1'length + vec2'length -1);
1254 (AST.SubtypeIn vectorTM
1255 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1256 [AST.ToRange (AST.PrimLit "0")
1257 (AST.PrimName (AST.NAttribute $
1258 AST.AttribName (AST.NSimple vec1Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:+:
1259 AST.PrimName (AST.NAttribute $
1260 AST.AttribName (AST.NSimple vec2Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1263 plusplusExpr = AST.NSimple resId AST.:=
1264 ((AST.PrimName $ AST.NSimple vec1Par) AST.:&:
1265 (AST.PrimName $ AST.NSimple vec2Par))
1266 plusplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1267 lengthTSpec = AST.Function (mkVHDLExtId lengthTId) [AST.IfaceVarDec vecPar vectorTM] naturalTM
1268 lengthTExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NAttribute $
1269 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))
1270 shiftlSpec = AST.Function (mkVHDLExtId shiftlId) [AST.IfaceVarDec vecPar vectorTM,
1271 AST.IfaceVarDec aPar elemTM ] vectorTM
1272 -- variable res : fsvec_x (0 to vec'length-1);
1275 (AST.SubtypeIn vectorTM
1276 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1277 [AST.ToRange (AST.PrimLit "0")
1278 (AST.PrimName (AST.NAttribute $
1279 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1280 (AST.PrimLit "1")) ]))
1282 -- res := a & init(vec)
1283 shiftlExpr = AST.NSimple resId AST.:=
1284 (AST.PrimName (AST.NSimple aPar) AST.:&:
1285 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1286 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1287 shiftlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1288 shiftrSpec = AST.Function (mkVHDLExtId shiftrId) [AST.IfaceVarDec vecPar vectorTM,
1289 AST.IfaceVarDec aPar elemTM ] vectorTM
1290 -- variable res : fsvec_x (0 to vec'length-1);
1293 (AST.SubtypeIn vectorTM
1294 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1295 [AST.ToRange (AST.PrimLit "0")
1296 (AST.PrimName (AST.NAttribute $
1297 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1298 (AST.PrimLit "1")) ]))
1300 -- res := tail(vec) & a
1301 shiftrExpr = AST.NSimple resId AST.:=
1302 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1303 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1304 (AST.PrimName (AST.NSimple aPar)))
1306 shiftrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1307 nullSpec = AST.Function (mkVHDLExtId nullId) [AST.IfaceVarDec vecPar vectorTM] booleanTM
1308 -- return vec'length = 0
1309 nullExpr = AST.ReturnSm (Just $
1310 AST.PrimName (AST.NAttribute $
1311 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:=:
1313 rotlSpec = AST.Function (mkVHDLExtId rotlId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1314 -- variable res : fsvec_x (0 to vec'length-1);
1317 (AST.SubtypeIn vectorTM
1318 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1319 [AST.ToRange (AST.PrimLit "0")
1320 (AST.PrimName (AST.NAttribute $
1321 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1322 (AST.PrimLit "1")) ]))
1324 -- if null(vec) then res := vec else res := last(vec) & init(vec)
1325 rotlExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1326 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1327 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1329 (Just $ AST.Else [rotlExprRet])
1331 AST.NSimple resId AST.:=
1332 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId lastId))
1333 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1334 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1335 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1336 rotlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1337 rotrSpec = AST.Function (mkVHDLExtId rotrId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1338 -- variable res : fsvec_x (0 to vec'length-1);
1341 (AST.SubtypeIn vectorTM
1342 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1343 [AST.ToRange (AST.PrimLit "0")
1344 (AST.PrimName (AST.NAttribute $
1345 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1346 (AST.PrimLit "1")) ]))
1348 -- if null(vec) then res := vec else res := tail(vec) & head(vec)
1349 rotrExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1350 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1351 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1353 (Just $ AST.Else [rotrExprRet])
1355 AST.NSimple resId AST.:=
1356 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1357 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1358 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId headId))
1359 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1360 rotrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1361 reverseSpec = AST.Function (mkVHDLExtId reverseId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1364 (AST.SubtypeIn vectorTM
1365 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1366 [AST.ToRange (AST.PrimLit "0")
1367 (AST.PrimName (AST.NAttribute $
1368 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1369 (AST.PrimLit "1")) ]))
1371 -- for i in 0 to res'range loop
1372 -- res(vec'length-i-1) := vec(i);
1375 AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple $ rangeId) Nothing) [reverseAssign]
1376 -- res(vec'length-i-1) := vec(i);
1377 reverseAssign = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [destExp]) AST.:=
1378 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar)
1379 [AST.PrimName $ AST.NSimple iId]))
1380 where destExp = AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar)
1381 (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1382 AST.PrimName (AST.NSimple iId) AST.:-:
1385 reverseRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1388 -----------------------------------------------------------------------------
1389 -- A table of builtin functions
1390 -----------------------------------------------------------------------------
1392 -- A function that generates VHDL for a builtin function
1393 type BuiltinBuilder =
1394 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
1395 -> CoreSyn.CoreBndr -- ^ The function called
1396 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
1397 -- dictionary arguments).
1398 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
1399 -- ^ The corresponding VHDL concurrent statements and entities
1402 -- A map of a builtin function to VHDL function builder
1403 type NameTable = Map.Map String (Int, BuiltinBuilder )
1405 -- | The builtin functions we support. Maps a name to an argument count and a
1406 -- builder function.
1407 globalNameTable :: NameTable
1408 globalNameTable = Map.fromList
1409 [ (exId , (2, genFCall True ) )
1410 , (replaceId , (3, genFCall False ) )
1411 , (headId , (1, genFCall True ) )
1412 , (lastId , (1, genFCall True ) )
1413 , (tailId , (1, genFCall False ) )
1414 , (initId , (1, genFCall False ) )
1415 , (takeId , (2, genFCall False ) )
1416 , (dropId , (2, genFCall False ) )
1417 , (selId , (4, genFCall False ) )
1418 , (plusgtId , (2, genFCall False ) )
1419 , (ltplusId , (2, genFCall False ) )
1420 , (plusplusId , (2, genFCall False ) )
1421 , (mapId , (2, genMap ) )
1422 , (zipWithId , (3, genZipWith ) )
1423 , (foldlId , (3, genFoldl ) )
1424 , (foldrId , (3, genFoldr ) )
1425 , (zipId , (2, genZip ) )
1426 , (unzipId , (1, genUnzip ) )
1427 , (shiftlId , (2, genFCall False ) )
1428 , (shiftrId , (2, genFCall False ) )
1429 , (rotlId , (1, genFCall False ) )
1430 , (rotrId , (1, genFCall False ) )
1431 , (concatId , (1, genConcat ) )
1432 , (reverseId , (1, genFCall False ) )
1433 , (iteratenId , (3, genIteraten ) )
1434 , (iterateId , (2, genIterate ) )
1435 , (generatenId , (3, genGeneraten ) )
1436 , (generateId , (2, genGenerate ) )
1437 , (emptyId , (0, genFCall False ) )
1438 , (singletonId , (1, genFCall False ) )
1439 , (copynId , (2, genFCall False ) )
1440 , (copyId , (1, genCopy ) )
1441 , (lengthTId , (1, genFCall False ) )
1442 , (nullId , (1, genFCall False ) )
1443 , (hwxorId , (2, genOperator2 AST.Xor ) )
1444 , (hwandId , (2, genOperator2 AST.And ) )
1445 , (hworId , (2, genOperator2 AST.Or ) )
1446 , (hwnotId , (1, genOperator1 AST.Not ) )
1447 , (equalityId , (2, genOperator2 (AST.:=:) ) )
1448 , (inEqualityId , (2, genOperator2 (AST.:/=:) ) )
1449 , (boolOrId , (2, genOperator2 AST.Or ) )
1450 , (boolAndId , (2, genOperator2 AST.And ) )
1451 , (plusId , (2, genOperator2 (AST.:+:) ) )
1452 , (timesId , (2, genOperator2 (AST.:*:) ) )
1453 , (negateId , (1, genNegation ) )
1454 , (minusId , (2, genOperator2 (AST.:-:) ) )
1455 , (fromSizedWordId , (1, genFromSizedWord ) )
1456 , (fromIntegerId , (1, genFromInteger ) )
1457 , (resizeId , (1, genResize ) )
1458 , (sizedIntId , (1, genSizedInt ) )
1459 , (smallIntegerId , (1, genFromInteger ) )
1460 , (fstId , (1, genFst ) )
1461 , (sndId , (1, genSnd ) )
1462 , (blockRAMId , (5, genBlockRAM ) )
1463 --, (tfvecId , (1, genTFVec ) )
1464 , (minimumId , (2, error $ "\nFunction name: \"minimum\" is used internally, use another name"))