1 module CLasH.VHDL.Generate where
4 import qualified Data.List as List
5 import qualified Data.Map as Map
6 import qualified Control.Monad as Monad
8 import qualified Data.Either as Either
10 import Data.Accessor.MonadState as MonadState
14 import qualified Language.VHDL.AST as AST
17 import qualified CoreSyn
21 import qualified IdInfo
22 import qualified Literal
24 import qualified TyCon
27 import CLasH.Translator.TranslatorTypes
28 import CLasH.VHDL.Constants
29 import CLasH.VHDL.VHDLTypes
30 import CLasH.VHDL.VHDLTools
31 import CLasH.Utils as Utils
32 import CLasH.Utils.Core.CoreTools
33 import CLasH.Utils.Pretty
34 import qualified CLasH.Normalize as Normalize
36 -----------------------------------------------------------------------------
37 -- Functions to generate VHDL for user-defined functions.
38 -----------------------------------------------------------------------------
40 -- | Create an entity for a given function
43 -> TranslatorSession Entity -- ^ The resulting entity
45 getEntity fname = Utils.makeCached fname tsEntities $ do
46 expr <- Normalize.getNormalized fname
47 -- Strip off lambda's, these will be arguments
48 let (args, letexpr) = CoreSyn.collectBinders expr
49 -- Generate ports for all non-empty types
50 args' <- catMaybesM $ mapM mkMap args
51 -- There must be a let at top level
52 let (CoreSyn.Let binds (CoreSyn.Var res)) = letexpr
53 -- TODO: Handle Nothing
55 let vhdl_id = mkVHDLBasicId $ varToString fname ++ "_" ++ varToStringUniq fname
56 let ent_decl = createEntityAST vhdl_id args' res'
57 let signature = Entity vhdl_id args' res' ent_decl
61 --[(SignalId, SignalInfo)]
63 -> TranslatorSession (Maybe Port)
66 --info = Maybe.fromMaybe
67 -- (error $ "Signal not found in the name map? This should not happen!")
69 -- Assume the bndr has a valid VHDL id already
72 error_msg = "\nVHDL.createEntity.mkMap: Can not create entity: " ++ pprString fname ++ "\nbecause no type can be created for port: " ++ pprString bndr
74 type_mark_maybe <- MonadState.lift tsType $ vhdl_ty error_msg ty
75 case type_mark_maybe of
76 Just type_mark -> return $ Just (id, type_mark)
77 Nothing -> return Nothing
80 -- | Create the VHDL AST for an entity
82 AST.VHDLId -- ^ The name of the function
83 -> [Port] -- ^ The entity's arguments
84 -> Maybe Port -- ^ The entity's result
85 -> AST.EntityDec -- ^ The entity with the ent_decl filled in as well
87 createEntityAST vhdl_id args res =
88 AST.EntityDec vhdl_id ports
90 -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
91 ports = map (mkIfaceSigDec AST.In) args
92 ++ (Maybe.maybeToList res_port)
94 -- Add a clk port if we have state
95 clk_port = AST.IfaceSigDec clockId AST.In std_logicTM
96 res_port = fmap (mkIfaceSigDec AST.Out) res
98 -- | Create a port declaration
100 AST.Mode -- ^ The mode for the port (In / Out)
101 -> Port -- ^ The id and type for the port
102 -> AST.IfaceSigDec -- ^ The resulting port declaration
104 mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
106 -- | Create an architecture for a given function
108 CoreSyn.CoreBndr -- ^ The function to get an architecture for
109 -> TranslatorSession (Architecture, [CoreSyn.CoreBndr])
110 -- ^ The architecture for this function
112 getArchitecture fname = Utils.makeCached fname tsArchitectures $ do
113 expr <- Normalize.getNormalized fname
114 signature <- getEntity fname
115 let entity_id = ent_id signature
116 -- Strip off lambda's, these will be arguments
117 let (args, letexpr) = CoreSyn.collectBinders expr
118 -- There must be a let at top level
119 let (CoreSyn.Let (CoreSyn.Rec binds) (CoreSyn.Var res)) = letexpr
121 -- Create signal declarations for all binders in the let expression, except
122 -- for the output port (that will already have an output port declared in
124 sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds)
125 let sig_decs = Maybe.catMaybes $ sig_dec_maybes
127 (statementss, used_entitiess) <- Monad.mapAndUnzipM mkConcSm binds
128 let statements = concat statementss
129 let used_entities = concat used_entitiess
130 let arch = AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
131 return (arch, used_entities)
133 procs = [] --map mkStateProcSm [] -- (makeStatePairs flatfunc)
134 procs' = map AST.CSPSm procs
135 -- mkSigDec only uses tsTypes from the state
138 -- | Transforms a core binding into a VHDL concurrent statement
140 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
141 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
142 -- ^ The corresponding VHDL concurrent statements and entities
146 -- Ignore Cast expressions, they should not longer have any meaning as long as
147 -- the type works out.
148 mkConcSm (bndr, CoreSyn.Cast expr ty) = mkConcSm (bndr, expr)
150 -- Simple a = b assignments are just like applications, but without arguments.
151 -- We can't just generate an unconditional assignment here, since b might be a
152 -- top level binding (e.g., a function with no arguments).
153 mkConcSm (bndr, CoreSyn.Var v) = do
154 genApplication (Left bndr) v []
156 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
157 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
158 let valargs = get_val_args (Var.varType f) args
159 genApplication (Left bndr) f (map Left valargs)
161 -- A single alt case must be a selector. This means thee scrutinee is a simple
162 -- variable, the alternative is a dataalt with a single non-wild binder that
164 mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt]))
165 -- Don't generate VHDL for substate extraction
166 | hasStateType bndr = return ([], [])
169 (CoreSyn.DataAlt dc, bndrs, (CoreSyn.Var sel_bndr)) -> do
170 bndrs' <- Monad.filterM hasNonEmptyType bndrs
171 case List.elemIndex sel_bndr bndrs' of
173 labels <- MonadState.lift tsType $ getFieldLabels (Id.idType scrut)
174 let label = labels!!i
175 let sel_name = mkSelectedName (varToVHDLName scrut) label
176 let sel_expr = AST.PrimName sel_name
177 return ([mkUncondAssign (Left bndr) sel_expr], [])
178 Nothing -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case:\n" ++ (pprString expr)
180 _ -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case:\n" ++ (pprString expr)
182 -- Multiple case alt are be conditional assignments and have only wild
183 -- binders in the alts and only variables in the case values and a variable
184 -- for a scrutinee. We check the constructor of the second alt, since the
185 -- first is the default case, if there is any.
186 mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) b ty [(_, _, CoreSyn.Var false), (con, _, CoreSyn.Var true)])) = do
187 scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut
188 let cond_expr = scrut' AST.:=: (altconToVHDLExpr con)
189 true_expr <- MonadState.lift tsType $ varToVHDLExpr true
190 false_expr <- MonadState.lift tsType $ varToVHDLExpr false
191 return ([mkCondAssign (Left bndr) cond_expr true_expr false_expr], [])
193 mkConcSm (_, (CoreSyn.Case (CoreSyn.Var _) _ _ alts)) = error "\nVHDL.mkConcSm: Not in normal form: Case statement with more than two alternatives"
194 mkConcSm (_, CoreSyn.Case _ _ _ _) = error "\nVHDL.mkConcSm: Not in normal form: Case statement has does not have a simple variable as scrutinee"
195 mkConcSm (bndr, expr) = error $ "\nVHDL.mkConcSM: Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
197 -----------------------------------------------------------------------------
198 -- Functions to generate VHDL for builtin functions
199 -----------------------------------------------------------------------------
201 -- | A function to wrap a builder-like function that expects its arguments to
203 genExprArgs wrap dst func args = do
204 args' <- argsToVHDLExprs args
207 -- | Turn the all lefts into VHDL Expressions.
208 argsToVHDLExprs :: [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.Expr]
209 argsToVHDLExprs = catMaybesM . (mapM argToVHDLExpr)
211 argToVHDLExpr :: Either CoreSyn.CoreExpr AST.Expr -> TranslatorSession (Maybe AST.Expr)
212 argToVHDLExpr (Left expr) = MonadState.lift tsType $ do
213 let errmsg = "Generate.argToVHDLExpr: Using non-representable type? Should not happen!"
214 ty_maybe <- vhdl_ty errmsg expr
217 vhdl_expr <- varToVHDLExpr $ exprToVar expr
218 return $ Just vhdl_expr
219 Nothing -> return $ Nothing
221 argToVHDLExpr (Right expr) = return $ Just expr
223 -- A function to wrap a builder-like function that generates no component
226 (dst -> func -> args -> TranslatorSession [AST.ConcSm])
227 -> (dst -> func -> args -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr]))
228 genNoInsts wrap dst func args = do
229 concsms <- wrap dst func args
232 -- | A function to wrap a builder-like function that expects its arguments to
235 (dst -> func -> [Var.Var] -> res)
236 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
237 genVarArgs wrap dst func args = wrap dst func args'
239 args' = map exprToVar exprargs
240 -- Check (rather crudely) that all arguments are CoreExprs
241 (exprargs, []) = Either.partitionEithers args
243 -- | A function to wrap a builder-like function that expects its arguments to
246 (dst -> func -> [Literal.Literal] -> res)
247 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
248 genLitArgs wrap dst func args = wrap dst func args'
250 args' = map exprToLit litargs
251 -- FIXME: Check if we were passed an CoreSyn.App
252 litargs = concat (map getLiterals exprargs)
253 (exprargs, []) = Either.partitionEithers args
255 -- | A function to wrap a builder-like function that produces an expression
256 -- and expects it to be assigned to the destination.
258 ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession AST.Expr)
259 -> ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession [AST.ConcSm])
260 genExprRes wrap dst func args = do
261 expr <- wrap dst func args
262 return $ [mkUncondAssign dst expr]
264 -- | Generate a binary operator application. The first argument should be a
265 -- constructor from the AST.Expr type, e.g. AST.And.
266 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
267 genOperator2 op = genNoInsts $ genExprArgs $ genExprRes (genOperator2' op)
268 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
269 genOperator2' op _ f [arg1, arg2] = return $ op arg1 arg2
271 -- | Generate a unary operator application
272 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
273 genOperator1 op = genNoInsts $ genExprArgs $ genExprRes (genOperator1' op)
274 genOperator1' :: (AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
275 genOperator1' op _ f [arg] = return $ op arg
277 -- | Generate a unary operator application
278 genNegation :: BuiltinBuilder
279 genNegation = genNoInsts $ genVarArgs $ genExprRes genNegation'
280 genNegation' :: dst -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession AST.Expr
281 genNegation' _ f [arg] = do
282 arg1 <- MonadState.lift tsType $ varToVHDLExpr arg
283 let ty = Var.varType arg
284 let (tycon, args) = Type.splitTyConApp ty
285 let name = Name.getOccString (TyCon.tyConName tycon)
287 "SizedInt" -> return $ AST.Neg arg1
288 otherwise -> error $ "\nGenerate.genNegation': Negation allowed for type: " ++ show name
290 -- | Generate a function call from the destination binder, function name and a
291 -- list of expressions (its arguments)
292 genFCall :: Bool -> BuiltinBuilder
293 genFCall switch = genNoInsts $ genExprArgs $ genExprRes (genFCall' switch)
294 genFCall' :: Bool -> Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
295 genFCall' switch (Left res) f args = do
296 let fname = varToString f
297 let el_ty = if switch then (Var.varType res) else ((tfvec_elem . Var.varType) res)
298 id <- MonadState.lift tsType $ vectorFunId el_ty fname
299 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
300 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
301 genFCall' _ (Right name) _ _ = error $ "\nGenerate.genFCall': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
303 genFromSizedWord :: BuiltinBuilder
304 genFromSizedWord = genNoInsts $ genExprArgs $ genExprRes genFromSizedWord'
305 genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
306 genFromSizedWord' (Left res) f args = do
307 let fname = varToString f
308 return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $
309 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
310 genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
312 genResize :: BuiltinBuilder
313 genResize = genNoInsts $ genExprArgs $ genExprRes genResize'
314 genResize' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
315 genResize' (Left res) f [arg] = do {
316 ; let { ty = Var.varType res
317 ; (tycon, args) = Type.splitTyConApp ty
318 ; name = Name.getOccString (TyCon.tyConName tycon)
320 ; len <- case name of
321 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
322 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
323 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId resizeId))
324 [Nothing AST.:=>: AST.ADExpr arg, Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
326 genResize' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
328 -- FIXME: I'm calling genLitArgs which is very specific function,
329 -- which needs to be fixed as well
330 genFromInteger :: BuiltinBuilder
331 genFromInteger = genNoInsts $ genLitArgs $ genExprRes genFromInteger'
332 genFromInteger' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [Literal.Literal] -> TranslatorSession AST.Expr
333 genFromInteger' (Left res) f lits = do {
334 ; let { ty = Var.varType res
335 ; (tycon, args) = Type.splitTyConApp ty
336 ; name = Name.getOccString (TyCon.tyConName tycon)
339 "RangedWord" -> return $ AST.PrimLit (show (last lits))
341 ; len <- case name of
342 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
343 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
344 "RangedWord" -> MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty)
345 ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId
346 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname))
347 [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
351 genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
353 genSizedInt :: BuiltinBuilder
354 genSizedInt = genFromInteger
357 -- | Generate a Builder for the builtin datacon TFVec
358 genTFVec :: BuiltinBuilder
359 genTFVec (Left res) f [Left (CoreSyn.Let (CoreSyn.Rec letBinders) letRes)] = do {
360 -- Generate Assignments for all the binders
361 ; letAssigns <- mapM genBinderAssign letBinders
362 -- Generate assignments for the result (which might be another let binding)
363 ; (resBinders,resAssignments) <- genResAssign letRes
364 -- Get all the Assigned binders
365 ; let assignedBinders = Maybe.catMaybes (map fst letAssigns)
366 -- Make signal names for all the assigned binders
367 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) (assignedBinders ++ resBinders)
368 -- Assign all the signals to the resulting vector
369 ; let { vecsigns = mkAggregateSignal sigs
370 ; vecassign = mkUncondAssign (Left res) vecsigns
372 -- Generate all the signal declaration for the assigned binders
373 ; sig_dec_maybes <- mapM mkSigDec (assignedBinders ++ resBinders)
374 ; let { sig_decs = map (AST.BDISD) (Maybe.catMaybes $ sig_dec_maybes)
375 -- Setup the VHDL Block
376 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
377 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) sig_decs ((concat (map snd letAssigns)) ++ resAssignments ++ [vecassign])
379 -- Return the block statement coressponding to the TFVec literal
380 ; return $ [AST.CSBSm block]
383 genBinderAssign :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -> TranslatorSession (Maybe CoreSyn.CoreBndr, [AST.ConcSm])
384 -- For now we only translate applications
385 genBinderAssign (bndr, app@(CoreSyn.App _ _)) = do
386 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
387 let valargs = get_val_args (Var.varType f) args
388 apps <- genApplication (Left bndr) f (map Left valargs)
389 return (Just bndr, apps)
390 genBinderAssign _ = return (Nothing,[])
391 genResAssign :: CoreSyn.CoreExpr -> TranslatorSession ([CoreSyn.CoreBndr], [AST.ConcSm])
392 genResAssign app@(CoreSyn.App _ letexpr) = do
394 (CoreSyn.Let (CoreSyn.Rec letbndrs) letres) -> do
395 letapps <- mapM genBinderAssign letbndrs
396 let bndrs = Maybe.catMaybes (map fst letapps)
397 let app = (map snd letapps)
398 (vars, apps) <- genResAssign letres
399 return ((bndrs ++ vars),((concat app) ++ apps))
400 otherwise -> return ([],[])
401 genResAssign _ = return ([],[])
403 genTFVec (Left res) f [Left app@(CoreSyn.App _ _)] = do {
404 ; let { elems = reduceCoreListToHsList app
405 -- Make signal names for all the binders
406 ; binders = map (\expr -> case expr of
408 otherwise -> error $ "\nGenerate.genTFVec: Cannot generate TFVec: "
409 ++ show res ++ ", with elems:\n" ++ show elems ++ "\n" ++ pprString elems) elems
411 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) binders
412 -- Assign all the signals to the resulting vector
413 ; let { vecsigns = mkAggregateSignal sigs
414 ; vecassign = mkUncondAssign (Left res) vecsigns
415 -- Setup the VHDL Block
416 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
417 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) [] [vecassign]
419 -- Return the block statement coressponding to the TFVec literal
420 ; return $ [AST.CSBSm block]
423 genTFVec (Left name) _ [Left xs] = error $ "\nGenerate.genTFVec: Cannot generate TFVec: " ++ show name ++ ", with elems:\n" ++ show xs ++ "\n" ++ pprString xs
425 genTFVec (Right name) _ _ = error $ "\nGenerate.genTFVec: Cannot generate TFVec assigned to VHDLName: " ++ show name
427 -- | Generate a generate statement for the builtin function "map"
428 genMap :: BuiltinBuilder
429 genMap (Left res) f [Left mapped_f, Left (CoreSyn.Var arg)] = do {
430 -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL
431 -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since
432 -- we must index it (which we couldn't if it was a VHDL Expr, since only
433 -- VHDLNames can be indexed).
434 -- Setup the generate scheme
435 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
436 -- TODO: Use something better than varToString
437 ; let { label = mkVHDLExtId ("mapVector" ++ (varToString res))
438 ; n_id = mkVHDLBasicId "n"
439 ; n_expr = idToVHDLExpr n_id
440 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
441 ; genScheme = AST.ForGn n_id range
442 -- Create the content of the generate statement: Applying the mapped_f to
443 -- each of the elements in arg, storing to each element in res
444 ; resname = mkIndexedName (varToVHDLName res) n_expr
445 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
446 ; (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f
447 ; valargs = get_val_args (Var.varType real_f) already_mapped_args
449 ; (app_concsms, used) <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr])
450 -- Return the generate statement
451 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
454 genMap' (Right name) _ _ = error $ "\nGenerate.genMap': Cannot generate map function call assigned to a VHDLName: " ++ show name
456 genZipWith :: BuiltinBuilder
457 genZipWith = genVarArgs genZipWith'
458 genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
459 genZipWith' (Left res) f args@[zipped_f, arg1, arg2] = do {
460 -- Setup the generate scheme
461 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
462 -- TODO: Use something better than varToString
463 ; let { label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
464 ; n_id = mkVHDLBasicId "n"
465 ; n_expr = idToVHDLExpr n_id
466 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
467 ; genScheme = AST.ForGn n_id range
468 -- Create the content of the generate statement: Applying the zipped_f to
469 -- each of the elements in arg1 and arg2, storing to each element in res
470 ; resname = mkIndexedName (varToVHDLName res) n_expr
471 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
472 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
474 ; (app_concsms, used) <- genApplication (Right resname) zipped_f [Right argexpr1, Right argexpr2]
475 -- Return the generate functions
476 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
479 genFoldl :: BuiltinBuilder
480 genFoldl = genFold True
482 genFoldr :: BuiltinBuilder
483 genFoldr = genFold False
485 genFold :: Bool -> BuiltinBuilder
486 genFold left = genVarArgs (genFold' left)
488 genFold' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
489 genFold' left res f args@[folded_f , start ,vec]= do
490 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty (Var.varType vec))
491 genFold'' len left res f args
493 genFold'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
494 -- Special case for an empty input vector, just assign start to res
495 genFold'' len left (Left res) _ [_, start, vec] | len == 0 = do
496 arg <- MonadState.lift tsType $ varToVHDLExpr start
497 return ([mkUncondAssign (Left res) arg], [])
499 genFold'' len left (Left res) f [folded_f, start, vec] = do
501 --len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
502 -- An expression for len-1
503 let len_min_expr = (AST.PrimLit $ show (len-1))
504 -- evec is (TFVec n), so it still needs an element type
505 let (nvec, _) = Type.splitAppTy (Var.varType vec)
506 -- Put the type of the start value in nvec, this will be the type of our
508 let tmp_ty = Type.mkAppTy nvec (Var.varType start)
509 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
510 -- TODO: Handle Nothing
511 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdl_ty error_msg tmp_ty
512 -- Setup the generate scheme
513 let gen_label = mkVHDLExtId ("foldlVector" ++ (varToString vec))
514 let block_label = mkVHDLExtId ("foldlVector" ++ (varToString res))
515 let gen_range = if left then AST.ToRange (AST.PrimLit "0") len_min_expr
516 else AST.DownRange len_min_expr (AST.PrimLit "0")
517 let gen_scheme = AST.ForGn n_id gen_range
518 -- Make the intermediate vector
519 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
520 -- Create the generate statement
521 cells' <- sequence [genFirstCell, genOtherCell]
522 let (cells, useds) = unzip cells'
523 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
524 -- Assign tmp[len-1] or tmp[0] to res
525 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr (if left then
526 (mkIndexedName tmp_name (AST.PrimLit $ show (len-1))) else
527 (mkIndexedName tmp_name (AST.PrimLit "0")))
528 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
529 return ([AST.CSBSm block], concat useds)
531 -- An id for the counter
532 n_id = mkVHDLBasicId "n"
533 n_cur = idToVHDLExpr n_id
534 -- An expression for previous n
535 n_prev = if left then (n_cur AST.:-: (AST.PrimLit "1"))
536 else (n_cur AST.:+: (AST.PrimLit "1"))
537 -- An id for the tmp result vector
538 tmp_id = mkVHDLBasicId "tmp"
539 tmp_name = AST.NSimple tmp_id
540 -- Generate parts of the fold
541 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
543 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
544 let cond_label = mkVHDLExtId "firstcell"
545 -- if n == 0 or n == len-1
546 let cond_scheme = AST.IfGn $ n_cur AST.:=: (if left then (AST.PrimLit "0")
547 else (AST.PrimLit $ show (len-1)))
548 -- Output to tmp[current n]
549 let resname = mkIndexedName tmp_name n_cur
551 argexpr1 <- MonadState.lift tsType $ varToVHDLExpr start
552 -- Input from vec[current n]
553 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
554 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
555 [Right argexpr1, Right argexpr2]
557 [Right argexpr2, Right argexpr1]
559 -- Return the conditional generate part
560 return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
563 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
564 let cond_label = mkVHDLExtId "othercell"
565 -- if n > 0 or n < len-1
566 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (if left then (AST.PrimLit "0")
567 else (AST.PrimLit $ show (len-1)))
568 -- Output to tmp[current n]
569 let resname = mkIndexedName tmp_name n_cur
570 -- Input from tmp[previous n]
571 let argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
572 -- Input from vec[current n]
573 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
574 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
575 [Right argexpr1, Right argexpr2]
577 [Right argexpr2, Right argexpr1]
579 -- Return the conditional generate part
580 return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
582 -- | Generate a generate statement for the builtin function "zip"
583 genZip :: BuiltinBuilder
584 genZip = genNoInsts $ genVarArgs genZip'
585 genZip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
586 genZip' (Left res) f args@[arg1, arg2] = do {
587 -- Setup the generate scheme
588 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
589 -- TODO: Use something better than varToString
590 ; let { label = mkVHDLExtId ("zipVector" ++ (varToString res))
591 ; n_id = mkVHDLBasicId "n"
592 ; n_expr = idToVHDLExpr n_id
593 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
594 ; genScheme = AST.ForGn n_id range
595 ; resname' = mkIndexedName (varToVHDLName res) n_expr
596 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
597 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
599 ; labels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType res))
600 ; let { resnameA = mkSelectedName resname' (labels!!0)
601 ; resnameB = mkSelectedName resname' (labels!!1)
602 ; resA_assign = mkUncondAssign (Right resnameA) argexpr1
603 ; resB_assign = mkUncondAssign (Right resnameB) argexpr2
605 -- Return the generate functions
606 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
609 -- | Generate a generate statement for the builtin function "unzip"
610 genUnzip :: BuiltinBuilder
611 genUnzip = genNoInsts $ genVarArgs genUnzip'
612 genUnzip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
613 genUnzip' (Left res) f args@[arg] = do {
614 -- Setup the generate scheme
615 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
616 -- TODO: Use something better than varToString
617 ; let { label = mkVHDLExtId ("unzipVector" ++ (varToString res))
618 ; n_id = mkVHDLBasicId "n"
619 ; n_expr = idToVHDLExpr n_id
620 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
621 ; genScheme = AST.ForGn n_id range
622 ; resname' = varToVHDLName res
623 ; argexpr' = mkIndexedName (varToVHDLName arg) n_expr
625 ; reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
626 ; arglabels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType arg))
627 ; let { resnameA = mkIndexedName (mkSelectedName resname' (reslabels!!0)) n_expr
628 ; resnameB = mkIndexedName (mkSelectedName resname' (reslabels!!1)) n_expr
629 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!0)
630 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!1)
631 ; resA_assign = mkUncondAssign (Right resnameA) argexprA
632 ; resB_assign = mkUncondAssign (Right resnameB) argexprB
634 -- Return the generate functions
635 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
638 genCopy :: BuiltinBuilder
639 genCopy = genNoInsts $ genVarArgs genCopy'
640 genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
641 genCopy' (Left res) f args@[arg] =
643 resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others)
644 (AST.PrimName $ (varToVHDLName arg))]
645 out_assign = mkUncondAssign (Left res) resExpr
649 genConcat :: BuiltinBuilder
650 genConcat = genNoInsts $ genVarArgs genConcat'
651 genConcat' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
652 genConcat' (Left res) f args@[arg] = do {
653 -- Setup the generate scheme
654 ; len1 <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
655 ; let (_, nvec) = Type.splitAppTy (Var.varType arg)
656 ; len2 <- MonadState.lift tsType $ tfp_to_int $ tfvec_len_ty nvec
657 -- TODO: Use something better than varToString
658 ; let { label = mkVHDLExtId ("concatVector" ++ (varToString res))
659 ; n_id = mkVHDLBasicId "n"
660 ; n_expr = idToVHDLExpr n_id
661 ; fromRange = n_expr AST.:*: (AST.PrimLit $ show len2)
662 ; genScheme = AST.ForGn n_id range
663 -- Create the content of the generate statement: Applying the mapped_f to
664 -- each of the elements in arg, storing to each element in res
665 ; toRange = (n_expr AST.:*: (AST.PrimLit $ show len2)) AST.:+: (AST.PrimLit $ show (len2-1))
666 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len1-1))
667 ; resname = vecSlice fromRange toRange
668 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
669 ; out_assign = mkUncondAssign (Right resname) argexpr
671 -- Return the generate statement
672 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [out_assign]]
675 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
676 (AST.ToRange init last))
678 genIteraten :: BuiltinBuilder
679 genIteraten dst f args = genIterate dst f (tail args)
681 genIterate :: BuiltinBuilder
682 genIterate = genIterateOrGenerate True
684 genGeneraten :: BuiltinBuilder
685 genGeneraten dst f args = genGenerate dst f (tail args)
687 genGenerate :: BuiltinBuilder
688 genGenerate = genIterateOrGenerate False
690 genIterateOrGenerate :: Bool -> BuiltinBuilder
691 genIterateOrGenerate iter = genVarArgs (genIterateOrGenerate' iter)
693 genIterateOrGenerate' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
694 genIterateOrGenerate' iter (Left res) f args = do
695 len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
696 genIterateOrGenerate'' len iter (Left res) f args
698 genIterateOrGenerate'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
699 -- Special case for an empty input vector, just assign start to res
700 genIterateOrGenerate'' len iter (Left res) _ [app_f, start] | len == 0 = return ([mkUncondAssign (Left res) (AST.PrimLit "\"\"")], [])
702 genIterateOrGenerate'' len iter (Left res) f [app_f, start] = do
704 -- len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
705 -- An expression for len-1
706 let len_min_expr = (AST.PrimLit $ show (len-1))
707 -- -- evec is (TFVec n), so it still needs an element type
708 -- let (nvec, _) = splitAppTy (Var.varType vec)
709 -- -- Put the type of the start value in nvec, this will be the type of our
710 -- -- temporary vector
711 let tmp_ty = Var.varType res
712 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
713 -- TODO: Handle Nothing
714 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdl_ty error_msg tmp_ty
715 -- Setup the generate scheme
716 let gen_label = mkVHDLExtId ("iterateVector" ++ (varToString start))
717 let block_label = mkVHDLExtId ("iterateVector" ++ (varToString res))
718 let gen_range = AST.ToRange (AST.PrimLit "0") len_min_expr
719 let gen_scheme = AST.ForGn n_id gen_range
720 -- Make the intermediate vector
721 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
722 -- Create the generate statement
723 cells' <- sequence [genFirstCell, genOtherCell]
724 let (cells, useds) = unzip cells'
725 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
726 -- Assign tmp[len-1] or tmp[0] to res
727 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr tmp_name
728 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
729 return ([AST.CSBSm block], concat useds)
731 -- An id for the counter
732 n_id = mkVHDLBasicId "n"
733 n_cur = idToVHDLExpr n_id
734 -- An expression for previous n
735 n_prev = n_cur AST.:-: (AST.PrimLit "1")
736 -- An id for the tmp result vector
737 tmp_id = mkVHDLBasicId "tmp"
738 tmp_name = AST.NSimple tmp_id
739 -- Generate parts of the fold
740 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
742 let cond_label = mkVHDLExtId "firstcell"
743 -- if n == 0 or n == len-1
744 let cond_scheme = AST.IfGn $ n_cur AST.:=: (AST.PrimLit "0")
745 -- Output to tmp[current n]
746 let resname = mkIndexedName tmp_name n_cur
748 argexpr <- MonadState.lift tsType $ varToVHDLExpr start
749 let startassign = mkUncondAssign (Right resname) argexpr
750 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
751 -- Return the conditional generate part
752 let gensm = AST.GenerateSm cond_label cond_scheme [] (if iter then
760 let cond_label = mkVHDLExtId "othercell"
761 -- if n > 0 or n < len-1
762 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (AST.PrimLit "0")
763 -- Output to tmp[current n]
764 let resname = mkIndexedName tmp_name n_cur
765 -- Input from tmp[previous n]
766 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
767 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
768 -- Return the conditional generate part
769 return $ (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
772 -----------------------------------------------------------------------------
773 -- Function to generate VHDL for applications
774 -----------------------------------------------------------------------------
776 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
777 -> CoreSyn.CoreBndr -- ^ The function to apply
778 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
779 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
780 -- ^ The corresponding VHDL concurrent statements and entities
782 genApplication dst f args = do
783 case Var.isGlobalId f of
785 top <- isTopLevelBinder f
788 -- Local binder that references a top level binding. Generate a
789 -- component instantiation.
790 signature <- getEntity f
791 args' <- argsToVHDLExprs args
792 let entity_id = ent_id signature
793 -- TODO: Using show here isn't really pretty, but we'll need some
794 -- unique-ish value...
795 let label = "comp_ins_" ++ (either show prettyShow) dst
796 portmaps <- mkAssocElems args' ((either varToVHDLName id) dst) signature
797 return ([mkComponentInst label entity_id portmaps], [f])
799 -- Not a top level binder, so this must be a local variable reference.
800 -- It should have a representable type (and thus, no arguments) and a
801 -- signal should be generated for it. Just generate an unconditional
803 f' <- MonadState.lift tsType $ varToVHDLExpr f
804 return $ ([mkUncondAssign dst f'], [])
805 True | not stateful ->
806 case Var.idDetails f of
807 IdInfo.DataConWorkId dc -> case dst of
808 -- It's a datacon. Create a record from its arguments.
810 -- We have the bndr, so we can get at the type
811 labels <- MonadState.lift tsType $ getFieldLabels (Var.varType bndr)
812 args' <- argsToVHDLExprs args
813 return $ (zipWith mkassign labels $ args', [])
815 mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
817 let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
818 mkUncondAssign (Right sel_name) arg
819 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconstructor application without an original binder"
820 IdInfo.DataConWrapId dc -> case dst of
821 -- It's a datacon. Create a record from its arguments.
823 case (Map.lookup (varToString f) globalNameTable) of
824 Just (arg_count, builder) ->
825 if length args == arg_count then
828 error $ "\nGenerate.genApplication(DataConWrapId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
829 Nothing -> error $ "\nGenerate.genApplication: Can't generate dataconwrapper: " ++ (show dc)
830 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconwrapper application without an original binder"
831 IdInfo.VanillaId -> do
832 -- It's a global value imported from elsewhere. These can be builtin
833 -- functions. Look up the function name in the name table and execute
834 -- the associated builder if there is any and the argument count matches
835 -- (this should always be the case if it typechecks, but just to be
837 case (Map.lookup (varToString f) globalNameTable) of
838 Just (arg_count, builder) ->
839 if length args == arg_count then
842 error $ "\nGenerate.genApplication(VanillaId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
844 top <- isTopLevelBinder f
847 -- Local binder that references a top level binding. Generate a
848 -- component instantiation.
849 signature <- getEntity f
850 args' <- argsToVHDLExprs args
851 let entity_id = ent_id signature
852 -- TODO: Using show here isn't really pretty, but we'll need some
853 -- unique-ish value...
854 let label = "comp_ins_" ++ (either show prettyShow) dst
855 portmaps <- mkAssocElems args' ((either varToVHDLName id) dst) signature
856 return ([mkComponentInst label entity_id portmaps], [f])
858 -- Not a top level binder, so this must be a local variable reference.
859 -- It should have a representable type (and thus, no arguments) and a
860 -- signal should be generated for it. Just generate an unconditional
862 -- FIXME : I DONT KNOW IF THE ABOVE COMMENT HOLDS HERE, SO FOR NOW JUST ERROR!
863 -- f' <- MonadState.lift tsType $ varToVHDLExpr f
864 -- return $ ([mkUncondAssign dst f'], [])
865 error $ ("\nGenerate.genApplication(VanillaId): Using function from another module that is not a known builtin: " ++ (pprString f))
866 IdInfo.ClassOpId cls -> do
867 -- FIXME: Not looking for what instance this class op is called for
868 -- Is quite stupid of course.
869 case (Map.lookup (varToString f) globalNameTable) of
870 Just (arg_count, builder) ->
871 if length args == arg_count then
874 error $ "\nGenerate.genApplication(ClassOpId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
875 Nothing -> error $ "\nGenerate.genApplication(ClassOpId): Using function from another module that is not a known builtin: " ++ pprString f
876 details -> error $ "\nGenerate.genApplication: Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
877 -- If we can't generate a component instantiation, and the destination is
878 -- a state type, don't generate anything.
881 -- Is our destination a state value?
882 stateful = case dst of
883 -- When our destination is a VHDL name, it won't have had a state type
885 -- Otherwise check its type
886 Left bndr -> hasStateType bndr
888 -----------------------------------------------------------------------------
889 -- Functions to generate functions dealing with vectors.
890 -----------------------------------------------------------------------------
892 -- Returns the VHDLId of the vector function with the given name for the given
893 -- element type. Generates -- this function if needed.
894 vectorFunId :: Type.Type -> String -> TypeSession AST.VHDLId
895 vectorFunId el_ty fname = do
896 let error_msg = "\nGenerate.vectorFunId: Can not construct vector function for element: " ++ pprString el_ty
897 -- TODO: Handle the Nothing case?
898 Just elemTM <- vhdl_ty error_msg el_ty
899 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
900 -- the VHDLState or something.
901 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
902 typefuns <- getA tsTypeFuns
903 case Map.lookup (OrdType el_ty, fname) typefuns of
904 -- Function already generated, just return it
905 Just (id, _) -> return id
906 -- Function not generated yet, generate it
908 let functions = genUnconsVectorFuns elemTM vectorTM
909 case lookup fname functions of
911 modA tsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, (fst body))
912 mapM_ (vectorFunId el_ty) (snd body)
914 Nothing -> error $ "\nGenerate.vectorFunId: I don't know how to generate vector function " ++ fname
916 function_id = mkVHDLExtId fname
918 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
919 -> AST.TypeMark -- ^ type of the vector
920 -> [(String, (AST.SubProgBody, [String]))]
921 genUnconsVectorFuns elemTM vectorTM =
922 [ (exId, (AST.SubProgBody exSpec [] [exExpr],[]))
923 , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr,replaceRet],[]))
924 , (lastId, (AST.SubProgBody lastSpec [] [lastExpr],[]))
925 , (initId, (AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet],[]))
926 , (minimumId, (AST.SubProgBody minimumSpec [] [minimumExpr],[]))
927 , (takeId, (AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet],[minimumId]))
928 , (dropId, (AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet],[]))
929 , (plusgtId, (AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet],[]))
930 , (emptyId, (AST.SubProgBody emptySpec [AST.SPVD emptyVar] [emptyExpr],[]))
931 , (singletonId, (AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet],[]))
932 , (copynId, (AST.SubProgBody copynSpec [AST.SPVD copynVar] [copynExpr],[]))
933 , (selId, (AST.SubProgBody selSpec [AST.SPVD selVar] [selFor, selRet],[]))
934 , (ltplusId, (AST.SubProgBody ltplusSpec [AST.SPVD ltplusVar] [ltplusExpr, ltplusRet],[]))
935 , (plusplusId, (AST.SubProgBody plusplusSpec [AST.SPVD plusplusVar] [plusplusExpr, plusplusRet],[]))
936 , (lengthTId, (AST.SubProgBody lengthTSpec [] [lengthTExpr],[]))
937 , (shiftlId, (AST.SubProgBody shiftlSpec [AST.SPVD shiftlVar] [shiftlExpr, shiftlRet], [initId]))
938 , (shiftrId, (AST.SubProgBody shiftrSpec [AST.SPVD shiftrVar] [shiftrExpr, shiftrRet], [tailId]))
939 , (nullId, (AST.SubProgBody nullSpec [] [nullExpr], []))
940 , (rotlId, (AST.SubProgBody rotlSpec [AST.SPVD rotlVar] [rotlExpr, rotlRet], [nullId, lastId, initId]))
941 , (rotrId, (AST.SubProgBody rotrSpec [AST.SPVD rotrVar] [rotrExpr, rotrRet], [nullId, tailId, headId]))
942 , (reverseId, (AST.SubProgBody reverseSpec [AST.SPVD reverseVar] [reverseFor, reverseRet], []))
945 ixPar = AST.unsafeVHDLBasicId "ix"
946 vecPar = AST.unsafeVHDLBasicId "vec"
947 vec1Par = AST.unsafeVHDLBasicId "vec1"
948 vec2Par = AST.unsafeVHDLBasicId "vec2"
949 nPar = AST.unsafeVHDLBasicId "n"
950 leftPar = AST.unsafeVHDLBasicId "nLeft"
951 rightPar = AST.unsafeVHDLBasicId "nRight"
952 iId = AST.unsafeVHDLBasicId "i"
954 aPar = AST.unsafeVHDLBasicId "a"
955 fPar = AST.unsafeVHDLBasicId "f"
956 sPar = AST.unsafeVHDLBasicId "s"
957 resId = AST.unsafeVHDLBasicId "res"
958 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
959 AST.IfaceVarDec ixPar naturalTM] elemTM
960 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
961 (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName $
963 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
964 , AST.IfaceVarDec iPar naturalTM
965 , AST.IfaceVarDec aPar elemTM
967 -- variable res : fsvec_x (0 to vec'length-1);
970 (AST.SubtypeIn vectorTM
971 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
972 [AST.ToRange (AST.PrimLit "0")
973 (AST.PrimName (AST.NAttribute $
974 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
975 (AST.PrimLit "1")) ]))
977 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
978 replaceExpr = AST.NSimple resId AST.:=
979 (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NSimple iPar) AST.:-: AST.PrimLit "1") AST.:&:
980 AST.PrimName (AST.NSimple aPar) AST.:&:
981 vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1")
982 ((AST.PrimName (AST.NAttribute $
983 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))
984 AST.:-: AST.PrimLit "1"))
985 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
986 vecSlice init last = AST.PrimName (AST.NSlice
989 (AST.ToRange init last)))
990 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
991 -- return vec(vec'length-1);
992 lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
994 [AST.PrimName (AST.NAttribute $
995 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
996 AST.:-: AST.PrimLit "1"])))
997 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
998 -- variable res : fsvec_x (0 to vec'length-2);
1001 (AST.SubtypeIn vectorTM
1002 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1003 [AST.ToRange (AST.PrimLit "0")
1004 (AST.PrimName (AST.NAttribute $
1005 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1006 (AST.PrimLit "2")) ]))
1008 -- resAST.:= vec(0 to vec'length-2)
1009 initExpr = AST.NSimple resId AST.:= (vecSlice
1011 (AST.PrimName (AST.NAttribute $
1012 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1013 AST.:-: AST.PrimLit "2"))
1014 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1015 minimumSpec = AST.Function (mkVHDLExtId minimumId) [AST.IfaceVarDec leftPar naturalTM,
1016 AST.IfaceVarDec rightPar naturalTM ] naturalTM
1017 minimumExpr = AST.IfSm ((AST.PrimName $ AST.NSimple leftPar) AST.:<: (AST.PrimName $ AST.NSimple rightPar))
1018 [AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple leftPar)]
1020 (Just $ AST.Else [minimumExprRet])
1021 where minimumExprRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple rightPar)
1022 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
1023 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1024 -- variable res : fsvec_x (0 to (minimum (n,vec'length))-1);
1025 minLength = AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId minimumId))
1026 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple nPar)
1027 ,Nothing AST.:=>: AST.ADExpr (AST.PrimName (AST.NAttribute $
1028 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]
1031 (AST.SubtypeIn vectorTM
1032 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1033 [AST.ToRange (AST.PrimLit "0")
1035 (AST.PrimLit "1")) ]))
1037 -- res AST.:= vec(0 to n-1)
1038 takeExpr = AST.NSimple resId AST.:=
1039 (vecSlice (AST.PrimLit "0")
1040 (minLength AST.:-: AST.PrimLit "1"))
1041 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1042 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
1043 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1044 -- variable res : fsvec_x (0 to vec'length-n-1);
1047 (AST.SubtypeIn vectorTM
1048 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1049 [AST.ToRange (AST.PrimLit "0")
1050 (AST.PrimName (AST.NAttribute $
1051 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1052 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
1054 -- res AST.:= vec(n to vec'length-1)
1055 dropExpr = AST.NSimple resId AST.:= (vecSlice
1056 (AST.PrimName $ AST.NSimple nPar)
1057 (AST.PrimName (AST.NAttribute $
1058 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1059 AST.:-: AST.PrimLit "1"))
1060 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1061 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
1062 AST.IfaceVarDec vecPar vectorTM] vectorTM
1063 -- variable res : fsvec_x (0 to vec'length);
1066 (AST.SubtypeIn vectorTM
1067 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1068 [AST.ToRange (AST.PrimLit "0")
1069 (AST.PrimName (AST.NAttribute $
1070 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1072 plusgtExpr = AST.NSimple resId AST.:=
1073 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
1074 (AST.PrimName $ AST.NSimple vecPar))
1075 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1076 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
1079 (AST.SubtypeIn vectorTM
1080 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1081 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "-1")]))
1083 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1084 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
1086 -- variable res : fsvec_x (0 to 0) := (others => a);
1089 (AST.SubtypeIn vectorTM
1090 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1091 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
1092 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1093 (AST.PrimName $ AST.NSimple aPar)])
1094 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1095 copynSpec = AST.Function (mkVHDLExtId copynId) [AST.IfaceVarDec nPar naturalTM,
1096 AST.IfaceVarDec aPar elemTM ] vectorTM
1097 -- variable res : fsvec_x (0 to n-1) := (others => a);
1100 (AST.SubtypeIn vectorTM
1101 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1102 [AST.ToRange (AST.PrimLit "0")
1103 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1104 (AST.PrimLit "1")) ]))
1105 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1106 (AST.PrimName $ AST.NSimple aPar)])
1108 copynExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1109 selSpec = AST.Function (mkVHDLExtId selId) [AST.IfaceVarDec fPar naturalTM,
1110 AST.IfaceVarDec sPar naturalTM,
1111 AST.IfaceVarDec nPar naturalTM,
1112 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1113 -- variable res : fsvec_x (0 to n-1);
1116 (AST.SubtypeIn vectorTM
1117 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1118 [AST.ToRange (AST.PrimLit "0")
1119 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1120 (AST.PrimLit "1")) ])
1123 -- for i res'range loop
1124 -- res(i) := vec(f+i*s);
1126 selFor = AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple $ rangeId) Nothing) [selAssign]
1127 -- res(i) := vec(f+i*s);
1128 selAssign = let origExp = AST.PrimName (AST.NSimple fPar) AST.:+:
1129 (AST.PrimName (AST.NSimple iId) AST.:*:
1130 AST.PrimName (AST.NSimple sPar)) in
1131 AST.NIndexed (AST.IndexedName (AST.NSimple resId) [AST.PrimName (AST.NSimple iId)]) AST.:=
1132 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [origExp]))
1134 selRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1135 ltplusSpec = AST.Function (mkVHDLExtId ltplusId) [AST.IfaceVarDec vecPar vectorTM,
1136 AST.IfaceVarDec aPar elemTM] vectorTM
1137 -- variable res : fsvec_x (0 to vec'length);
1140 (AST.SubtypeIn vectorTM
1141 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1142 [AST.ToRange (AST.PrimLit "0")
1143 (AST.PrimName (AST.NAttribute $
1144 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1146 ltplusExpr = AST.NSimple resId AST.:=
1147 ((AST.PrimName $ AST.NSimple vecPar) AST.:&:
1148 (AST.PrimName $ AST.NSimple aPar))
1149 ltplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1150 plusplusSpec = AST.Function (mkVHDLExtId plusplusId) [AST.IfaceVarDec vec1Par vectorTM,
1151 AST.IfaceVarDec vec2Par vectorTM]
1153 -- variable res : fsvec_x (0 to vec1'length + vec2'length -1);
1156 (AST.SubtypeIn vectorTM
1157 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1158 [AST.ToRange (AST.PrimLit "0")
1159 (AST.PrimName (AST.NAttribute $
1160 AST.AttribName (AST.NSimple vec1Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:+:
1161 AST.PrimName (AST.NAttribute $
1162 AST.AttribName (AST.NSimple vec2Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1165 plusplusExpr = AST.NSimple resId AST.:=
1166 ((AST.PrimName $ AST.NSimple vec1Par) AST.:&:
1167 (AST.PrimName $ AST.NSimple vec2Par))
1168 plusplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1169 lengthTSpec = AST.Function (mkVHDLExtId lengthTId) [AST.IfaceVarDec vecPar vectorTM] naturalTM
1170 lengthTExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NAttribute $
1171 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))
1172 shiftlSpec = AST.Function (mkVHDLExtId shiftlId) [AST.IfaceVarDec vecPar vectorTM,
1173 AST.IfaceVarDec aPar elemTM ] vectorTM
1174 -- variable res : fsvec_x (0 to vec'length-1);
1177 (AST.SubtypeIn vectorTM
1178 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1179 [AST.ToRange (AST.PrimLit "0")
1180 (AST.PrimName (AST.NAttribute $
1181 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1182 (AST.PrimLit "1")) ]))
1184 -- res := a & init(vec)
1185 shiftlExpr = AST.NSimple resId AST.:=
1186 (AST.PrimName (AST.NSimple aPar) AST.:&:
1187 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1188 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1189 shiftlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1190 shiftrSpec = AST.Function (mkVHDLExtId shiftrId) [AST.IfaceVarDec vecPar vectorTM,
1191 AST.IfaceVarDec aPar elemTM ] vectorTM
1192 -- variable res : fsvec_x (0 to vec'length-1);
1195 (AST.SubtypeIn vectorTM
1196 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1197 [AST.ToRange (AST.PrimLit "0")
1198 (AST.PrimName (AST.NAttribute $
1199 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1200 (AST.PrimLit "1")) ]))
1202 -- res := tail(vec) & a
1203 shiftrExpr = AST.NSimple resId AST.:=
1204 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1205 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1206 (AST.PrimName (AST.NSimple aPar)))
1208 shiftrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1209 nullSpec = AST.Function (mkVHDLExtId nullId) [AST.IfaceVarDec vecPar vectorTM] booleanTM
1210 -- return vec'length = 0
1211 nullExpr = AST.ReturnSm (Just $
1212 AST.PrimName (AST.NAttribute $
1213 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:=:
1215 rotlSpec = AST.Function (mkVHDLExtId rotlId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1216 -- variable res : fsvec_x (0 to vec'length-1);
1219 (AST.SubtypeIn vectorTM
1220 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1221 [AST.ToRange (AST.PrimLit "0")
1222 (AST.PrimName (AST.NAttribute $
1223 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1224 (AST.PrimLit "1")) ]))
1226 -- if null(vec) then res := vec else res := last(vec) & init(vec)
1227 rotlExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1228 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1229 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1231 (Just $ AST.Else [rotlExprRet])
1233 AST.NSimple resId AST.:=
1234 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId lastId))
1235 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1236 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1237 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1238 rotlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1239 rotrSpec = AST.Function (mkVHDLExtId rotrId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1240 -- variable res : fsvec_x (0 to vec'length-1);
1243 (AST.SubtypeIn vectorTM
1244 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1245 [AST.ToRange (AST.PrimLit "0")
1246 (AST.PrimName (AST.NAttribute $
1247 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1248 (AST.PrimLit "1")) ]))
1250 -- if null(vec) then res := vec else res := tail(vec) & head(vec)
1251 rotrExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1252 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1253 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1255 (Just $ AST.Else [rotrExprRet])
1257 AST.NSimple resId AST.:=
1258 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1259 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1260 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId headId))
1261 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1262 rotrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1263 reverseSpec = AST.Function (mkVHDLExtId reverseId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1266 (AST.SubtypeIn vectorTM
1267 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1268 [AST.ToRange (AST.PrimLit "0")
1269 (AST.PrimName (AST.NAttribute $
1270 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1271 (AST.PrimLit "1")) ]))
1273 -- for i in 0 to res'range loop
1274 -- res(vec'length-i-1) := vec(i);
1277 AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple $ rangeId) Nothing) [reverseAssign]
1278 -- res(vec'length-i-1) := vec(i);
1279 reverseAssign = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [destExp]) AST.:=
1280 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar)
1281 [AST.PrimName $ AST.NSimple iId]))
1282 where destExp = AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar)
1283 (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1284 AST.PrimName (AST.NSimple iId) AST.:-:
1287 reverseRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1290 -----------------------------------------------------------------------------
1291 -- A table of builtin functions
1292 -----------------------------------------------------------------------------
1294 -- A function that generates VHDL for a builtin function
1295 type BuiltinBuilder =
1296 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
1297 -> CoreSyn.CoreBndr -- ^ The function called
1298 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
1299 -- dictionary arguments).
1300 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
1301 -- ^ The corresponding VHDL concurrent statements and entities
1304 -- A map of a builtin function to VHDL function builder
1305 type NameTable = Map.Map String (Int, BuiltinBuilder )
1307 -- | The builtin functions we support. Maps a name to an argument count and a
1308 -- builder function.
1309 globalNameTable :: NameTable
1310 globalNameTable = Map.fromList
1311 [ (exId , (2, genFCall True ) )
1312 , (replaceId , (3, genFCall False ) )
1313 , (headId , (1, genFCall True ) )
1314 , (lastId , (1, genFCall True ) )
1315 , (tailId , (1, genFCall False ) )
1316 , (initId , (1, genFCall False ) )
1317 , (takeId , (2, genFCall False ) )
1318 , (dropId , (2, genFCall False ) )
1319 , (selId , (4, genFCall False ) )
1320 , (plusgtId , (2, genFCall False ) )
1321 , (ltplusId , (2, genFCall False ) )
1322 , (plusplusId , (2, genFCall False ) )
1323 , (mapId , (2, genMap ) )
1324 , (zipWithId , (3, genZipWith ) )
1325 , (foldlId , (3, genFoldl ) )
1326 , (foldrId , (3, genFoldr ) )
1327 , (zipId , (2, genZip ) )
1328 , (unzipId , (1, genUnzip ) )
1329 , (shiftlId , (2, genFCall False ) )
1330 , (shiftrId , (2, genFCall False ) )
1331 , (rotlId , (1, genFCall False ) )
1332 , (rotrId , (1, genFCall False ) )
1333 , (concatId , (1, genConcat ) )
1334 , (reverseId , (1, genFCall False ) )
1335 , (iteratenId , (3, genIteraten ) )
1336 , (iterateId , (2, genIterate ) )
1337 , (generatenId , (3, genGeneraten ) )
1338 , (generateId , (2, genGenerate ) )
1339 , (emptyId , (0, genFCall False ) )
1340 , (singletonId , (1, genFCall False ) )
1341 , (copynId , (2, genFCall False ) )
1342 , (copyId , (1, genCopy ) )
1343 , (lengthTId , (1, genFCall False ) )
1344 , (nullId , (1, genFCall False ) )
1345 , (hwxorId , (2, genOperator2 AST.Xor ) )
1346 , (hwandId , (2, genOperator2 AST.And ) )
1347 , (hworId , (2, genOperator2 AST.Or ) )
1348 , (hwnotId , (1, genOperator1 AST.Not ) )
1349 , (plusId , (2, genOperator2 (AST.:+:) ) )
1350 , (timesId , (2, genOperator2 (AST.:*:) ) )
1351 , (negateId , (1, genNegation ) )
1352 , (minusId , (2, genOperator2 (AST.:-:) ) )
1353 , (fromSizedWordId , (1, genFromSizedWord ) )
1354 , (fromIntegerId , (1, genFromInteger ) )
1355 , (resizeId , (1, genResize ) )
1356 , (sizedIntId , (1, genSizedInt ) )
1357 , (smallIntegerId , (1, genFromInteger ) )
1358 --, (tfvecId , (1, genTFVec ) )
1359 , (minimumId , (2, error $ "\nFunction name: \"minimum\" is used internally, use another name"))