1 module CLasH.VHDL.Generate where
4 import qualified Data.List as List
5 import qualified Data.Map as Map
6 import qualified Control.Monad as Monad
8 import qualified Data.Either as Either
9 import qualified Data.Accessor.Monad.Trans.State as MonadState
12 import qualified Language.VHDL.AST as AST
15 import qualified CoreSyn
19 import qualified IdInfo
20 import qualified Literal
22 import qualified TyCon
25 import CLasH.Translator.TranslatorTypes
26 import CLasH.VHDL.Constants
27 import CLasH.VHDL.VHDLTypes
28 import CLasH.VHDL.VHDLTools
30 import CLasH.Utils.Core.CoreTools
31 import CLasH.Utils.Pretty
32 import qualified CLasH.Normalize as Normalize
34 -----------------------------------------------------------------------------
35 -- Functions to generate VHDL for user-defined functions.
36 -----------------------------------------------------------------------------
38 -- | Create an entity for a given function
41 -> TranslatorSession Entity -- ^ The resulting entity
43 getEntity fname = makeCached fname tsEntities $ do
44 expr <- Normalize.getNormalized fname
45 -- Split the normalized expression
46 let (args, binds, res) = Normalize.splitNormalized expr
47 -- Generate ports for all non-empty types
48 args' <- catMaybesM $ mapM mkMap args
49 -- TODO: Handle Nothing
51 count <- MonadState.get tsEntityCounter
52 let vhdl_id = mkVHDLBasicId $ varToString fname ++ "Component_" ++ show count
53 MonadState.set tsEntityCounter (count + 1)
54 let ent_decl = createEntityAST vhdl_id args' res'
55 let signature = Entity vhdl_id args' res' ent_decl
59 --[(SignalId, SignalInfo)]
61 -> TranslatorSession (Maybe Port)
64 --info = Maybe.fromMaybe
65 -- (error $ "Signal not found in the name map? This should not happen!")
67 -- Assume the bndr has a valid VHDL id already
70 error_msg = "\nVHDL.createEntity.mkMap: Can not create entity: " ++ pprString fname ++ "\nbecause no type can be created for port: " ++ pprString bndr
72 type_mark_maybe <- MonadState.lift tsType $ vhdlTy error_msg ty
73 case type_mark_maybe of
74 Just type_mark -> return $ Just (id, type_mark)
75 Nothing -> return Nothing
78 -- | Create the VHDL AST for an entity
80 AST.VHDLId -- ^ The name of the function
81 -> [Port] -- ^ The entity's arguments
82 -> Maybe Port -- ^ The entity's result
83 -> AST.EntityDec -- ^ The entity with the ent_decl filled in as well
85 createEntityAST vhdl_id args res =
86 AST.EntityDec vhdl_id ports
88 -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
89 ports = map (mkIfaceSigDec AST.In) args
90 ++ (Maybe.maybeToList res_port)
91 ++ [clk_port,resetn_port]
92 -- Add a clk port if we have state
93 clk_port = AST.IfaceSigDec clockId AST.In std_logicTM
94 resetn_port = AST.IfaceSigDec resetId AST.In std_logicTM
95 res_port = fmap (mkIfaceSigDec AST.Out) res
97 -- | Create a port declaration
99 AST.Mode -- ^ The mode for the port (In / Out)
100 -> Port -- ^ The id and type for the port
101 -> AST.IfaceSigDec -- ^ The resulting port declaration
103 mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
105 -- | Create an architecture for a given function
107 CoreSyn.CoreBndr -- ^ The function to get an architecture for
108 -> TranslatorSession (Architecture, [CoreSyn.CoreBndr])
109 -- ^ The architecture for this function
111 getArchitecture fname = makeCached fname tsArchitectures $ do
112 expr <- Normalize.getNormalized fname
113 -- Split the normalized expression
114 let (args, binds, res) = Normalize.splitNormalized expr
116 -- Get the entity for this function
117 signature <- getEntity fname
118 let entity_id = ent_id signature
120 -- Create signal declarations for all binders in the let expression, except
121 -- for the output port (that will already have an output port declared in
123 sig_dec_maybes <- mapM (mkSigDec . fst) (filter ((/=res).fst) binds)
124 let sig_decs = Maybe.catMaybes sig_dec_maybes
125 -- Process each bind, resulting in info about state variables and concurrent
127 (state_vars, sms) <- Monad.mapAndUnzipM dobind binds
128 let (in_state_maybes, out_state_maybes) = unzip state_vars
129 let (statementss, used_entitiess) = unzip sms
130 -- Get initial state, if it's there
131 initSmap <- MonadState.get tsInitStates
132 let init_state = Map.lookup fname initSmap
133 -- Create a state proc, if needed
134 (state_proc, resbndr) <- case (Maybe.catMaybes in_state_maybes, Maybe.catMaybes out_state_maybes, init_state) of
135 ([in_state], [out_state], Nothing) -> do
136 nonEmpty <- hasNonEmptyType in_state
137 if nonEmpty then error ("No initial state defined for: " ++ show fname) else return ([],[])
138 ([in_state], [out_state], Just resetval) -> mkStateProcSm (in_state, out_state,resetval)
139 ([], [], Just _) -> error $ "Initial state defined for state-less function: " ++ show fname
140 ([], [], Nothing) -> return ([],[])
141 (ins, outs, res) -> error $ "Weird use of state in " ++ show fname ++ ". In: " ++ show ins ++ " Out: " ++ show outs
142 -- Join the create statements and the (optional) state_proc
143 let statements = concat statementss ++ state_proc
144 -- Create the architecture
145 let arch = AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) statements
146 let used_entities = (concat used_entitiess) ++ resbndr
147 return (arch, used_entities)
149 dobind :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The bind to process
150 -> TranslatorSession ((Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreBndr), ([AST.ConcSm], [CoreSyn.CoreBndr]))
151 -- ^ ((Input state variable, output state variable), (statements, used entities))
152 -- newtype unpacking is just a cast
153 dobind (bndr, unpacked@(CoreSyn.Cast packed coercion))
154 | hasStateType packed && not (hasStateType unpacked)
155 = return ((Just bndr, Nothing), ([], []))
156 -- With simplCore, newtype packing is just a cast
157 dobind (bndr, packed@(CoreSyn.Cast unpacked@(CoreSyn.Var state) coercion))
158 | hasStateType packed && not (hasStateType unpacked)
159 = return ((Nothing, Just state), ([], []))
160 -- Without simplCore, newtype packing uses a data constructor
161 dobind (bndr, (CoreSyn.App (CoreSyn.App (CoreSyn.Var con) (CoreSyn.Type _)) (CoreSyn.Var state)))
163 = return ((Nothing, Just state), ([], []))
164 -- Anything else is handled by mkConcSm
167 return ((Nothing, Nothing), sms)
170 (CoreSyn.CoreBndr, CoreSyn.CoreBndr, CoreSyn.CoreBndr) -- ^ The current state, new state and reset variables
171 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr]) -- ^ The resulting statements
172 mkStateProcSm (old, new, res) = do
173 let error_msg = "\nVHDL.mkSigDec: Can not make signal declaration for type: \n" ++ pprString res
174 type_mark_old_maybe <- MonadState.lift tsType $ vhdlTy error_msg (Var.varType old)
175 let type_mark_old = Maybe.fromJust type_mark_old_maybe
176 type_mark_res_maybe <- MonadState.lift tsType $ vhdlTy error_msg (Var.varType res)
177 let type_mark_res' = Maybe.fromJust type_mark_res_maybe
178 let type_mark_res = if type_mark_old == type_mark_res' then
181 error $ "Initial state has different type than state type, state type: " ++ show type_mark_old ++ ", init type: " ++ show type_mark_res'
182 let resvalid = mkVHDLExtId $ varToString res ++ "val"
183 let resvaldec = AST.BDISD $ AST.SigDec resvalid type_mark_res Nothing
184 let reswform = AST.Wform [AST.WformElem (AST.PrimName $ AST.NSimple resvalid) Nothing]
185 let res_assign = AST.SigAssign (varToVHDLName old) reswform
186 let blocklabel = mkVHDLBasicId "state"
187 let statelabel = mkVHDLBasicId "stateupdate"
188 let rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
189 let wform = AST.Wform [AST.WformElem (AST.PrimName $ varToVHDLName new) Nothing]
190 let clk_assign = AST.SigAssign (varToVHDLName old) wform
191 let rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clockId)]
192 let resetn_is_low = (AST.PrimName $ AST.NSimple resetId) AST.:=: (AST.PrimLit "'0'")
193 signature <- getEntity res
194 let entity_id = ent_id signature
195 let reslabel = "resetval_" ++ ((prettyShow . varToVHDLName) res)
196 let portmaps = mkAssocElems [] (AST.NSimple resvalid) signature
197 let reset_statement = mkComponentInst reslabel entity_id portmaps
198 let clk_statement = [AST.ElseIf rising_edge_clk [clk_assign]]
199 let statement = AST.IfSm resetn_is_low [res_assign] clk_statement Nothing
200 let stateupdate = AST.CSPSm $ AST.ProcSm statelabel [clockId,resetId,resvalid] [statement]
201 let block = AST.CSBSm $ AST.BlockSm blocklabel [] (AST.PMapAspect []) [resvaldec] [reset_statement,stateupdate]
202 return ([block],[res])
204 -- | Transforms a core binding into a VHDL concurrent statement
206 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
207 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
208 -- ^ The corresponding VHDL concurrent statements and entities
212 -- Ignore Cast expressions, they should not longer have any meaning as long as
213 -- the type works out. Throw away state repacking
214 mkConcSm (bndr, to@(CoreSyn.Cast from ty))
215 | hasStateType to && hasStateType from
217 mkConcSm (bndr, CoreSyn.Cast expr ty) = mkConcSm (bndr, expr)
219 -- Simple a = b assignments are just like applications, but without arguments.
220 -- We can't just generate an unconditional assignment here, since b might be a
221 -- top level binding (e.g., a function with no arguments).
222 mkConcSm (bndr, CoreSyn.Var v) =
223 genApplication (Left bndr) v []
225 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
226 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
227 let valargs = get_val_args (Var.varType f) args
228 genApplication (Left bndr) f (map Left valargs)
230 -- A single alt case must be a selector. This means the scrutinee is a simple
231 -- variable, the alternative is a dataalt with a single non-wild binder that
233 mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt]))
234 -- Don't generate VHDL for substate extraction
235 | hasStateType bndr = return ([], [])
238 (CoreSyn.DataAlt dc, bndrs, (CoreSyn.Var sel_bndr)) -> do
239 bndrs' <- Monad.filterM hasNonEmptyType bndrs
240 case List.elemIndex sel_bndr bndrs' of
242 htypeScrt <- MonadState.lift tsType $ mkHTypeEither (Var.varType scrut)
243 htypeBndr <- MonadState.lift tsType $ mkHTypeEither (Var.varType bndr)
244 case htypeScrt == htypeBndr of
246 let sel_name = varToVHDLName scrut
247 let sel_expr = AST.PrimName sel_name
248 return ([mkUncondAssign (Left bndr) sel_expr], [])
251 Right (AggrType _ _) -> do
252 labels <- MonadState.lift tsType $ getFieldLabels (Id.idType scrut)
253 let label = labels!!i
254 let sel_name = mkSelectedName (varToVHDLName scrut) label
255 let sel_expr = AST.PrimName sel_name
256 return ([mkUncondAssign (Left bndr) sel_expr], [])
257 _ -> do -- error $ "DIE!"
258 let sel_name = varToVHDLName scrut
259 let sel_expr = AST.PrimName sel_name
260 return ([mkUncondAssign (Left bndr) sel_expr], [])
261 Nothing -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case:\n" ++ (pprString expr)
263 _ -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case:\n" ++ (pprString expr)
265 -- Multiple case alt are be conditional assignments and have only wild
266 -- binders in the alts and only variables in the case values and a variable
267 -- for a scrutinee. We check the constructor of the second alt, since the
268 -- first is the default case, if there is any.
270 -- mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) b ty [(_, _, CoreSyn.Var false), (con, _, CoreSyn.Var true)])) = do
271 -- scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut
272 -- altcon <- MonadState.lift tsType $ altconToVHDLExpr con
273 -- let cond_expr = scrut' AST.:=: altcon
274 -- true_expr <- MonadState.lift tsType $ varToVHDLExpr true
275 -- false_expr <- MonadState.lift tsType $ varToVHDLExpr false
276 -- return ([mkCondAssign (Left bndr) cond_expr true_expr false_expr], [])
277 mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) _ _ (alt:alts))) = do --error "\nVHDL.mkConcSm: Not in normal form: Case statement with more than two alternatives"
278 scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut
279 -- Omit first condition, which is the default
280 altcons <- MonadState.lift tsType $ mapM (altconToVHDLExpr . (\(con,_,_) -> con)) alts
281 let cond_exprs = map (\x -> scrut' AST.:=: x) altcons
282 -- Rotate expressions to the left, so that the expression related to the default case is the last
283 exprs <- MonadState.lift tsType $ mapM (varToVHDLExpr . (\(_,_,CoreSyn.Var expr) -> expr)) (alts ++ [alt])
284 return ([mkAltsAssign (Left bndr) cond_exprs exprs], [])
286 mkConcSm (_, CoreSyn.Case _ _ _ _) = error "\nVHDL.mkConcSm: Not in normal form: Case statement has does not have a simple variable as scrutinee"
287 mkConcSm (bndr, expr) = error $ "\nVHDL.mkConcSM: Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
289 -----------------------------------------------------------------------------
290 -- Functions to generate VHDL for builtin functions
291 -----------------------------------------------------------------------------
293 -- | A function to wrap a builder-like function that expects its arguments to
295 genExprArgs wrap dst func args = do
296 args' <- argsToVHDLExprs args
299 -- | Turn the all lefts into VHDL Expressions.
300 argsToVHDLExprs :: [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.Expr]
301 argsToVHDLExprs = catMaybesM . (mapM argToVHDLExpr)
303 argToVHDLExpr :: Either CoreSyn.CoreExpr AST.Expr -> TranslatorSession (Maybe AST.Expr)
304 argToVHDLExpr (Left expr) = MonadState.lift tsType $ do
305 let errmsg = "Generate.argToVHDLExpr: Using non-representable type? Should not happen!"
306 ty_maybe <- vhdlTy errmsg expr
309 vhdl_expr <- varToVHDLExpr $ exprToVar expr
310 return $ Just vhdl_expr
311 Nothing -> return Nothing
313 argToVHDLExpr (Right expr) = return $ Just expr
315 -- A function to wrap a builder-like function that generates no component
318 (dst -> func -> args -> TranslatorSession [AST.ConcSm])
319 -> (dst -> func -> args -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr]))
320 genNoInsts wrap dst func args = do
321 concsms <- wrap dst func args
324 -- | A function to wrap a builder-like function that expects its arguments to
327 (dst -> func -> [Var.Var] -> res)
328 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
329 genVarArgs wrap dst func args = wrap dst func args'
331 args' = map exprToVar exprargs
332 -- Check (rather crudely) that all arguments are CoreExprs
333 (exprargs, []) = Either.partitionEithers args
335 -- | A function to wrap a builder-like function that expects its arguments to
338 (dst -> func -> [Literal.Literal] -> TranslatorSession [AST.ConcSm])
339 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.ConcSm])
340 genLitArgs wrap dst func args = do
341 hscenv <- MonadState.lift tsType $ MonadState.get tsHscEnv
342 let (exprargs, []) = Either.partitionEithers args
343 -- FIXME: Check if we were passed an CoreSyn.App
344 let litargs = concatMap (getLiterals hscenv) exprargs
345 let args' = map exprToLit litargs
348 -- | A function to wrap a builder-like function that produces an expression
349 -- and expects it to be assigned to the destination.
351 ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession AST.Expr)
352 -> ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession [AST.ConcSm])
353 genExprRes wrap dst func args = do
354 expr <- wrap dst func args
355 return [mkUncondAssign dst expr]
357 -- | Generate a binary operator application. The first argument should be a
358 -- constructor from the AST.Expr type, e.g. AST.And.
359 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
360 genOperator2 op = genNoInsts $ genExprArgs $ genExprRes (genOperator2' op)
361 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
362 genOperator2' op _ f [arg1, arg2] = return $ op arg1 arg2
364 -- | Generate a unary operator application
365 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
366 genOperator1 op = genNoInsts $ genExprArgs $ genExprRes (genOperator1' op)
367 genOperator1' :: (AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
368 genOperator1' op _ f [arg] = return $ op arg
370 -- | Generate a unary operator application
371 genNegation :: BuiltinBuilder
372 genNegation = genNoInsts $ genVarArgs $ genExprRes genNegation'
373 genNegation' :: dst -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession AST.Expr
374 genNegation' _ f [arg] = do
375 arg1 <- MonadState.lift tsType $ varToVHDLExpr arg
376 let ty = Var.varType arg
377 let (tycon, args) = Type.splitTyConApp ty
378 let name = Name.getOccString (TyCon.tyConName tycon)
380 "SizedInt" -> return $ AST.Neg arg1
381 otherwise -> error $ "\nGenerate.genNegation': Negation not allowed for type: " ++ show name
383 -- | Generate a function call from the destination binder, function name and a
384 -- list of expressions (its arguments)
385 genFCall :: Bool -> BuiltinBuilder
386 genFCall switch = genNoInsts $ genExprArgs $ genExprRes (genFCall' switch)
387 genFCall' :: Bool -> Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
388 genFCall' switch (Left res) f args = do
389 let fname = varToString f
390 let el_ty = if switch then (Var.varType res) else ((tfvec_elem . Var.varType) res)
391 id <- MonadState.lift tsType $ vectorFunId el_ty fname
392 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
393 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
394 genFCall' _ (Right name) _ _ = error $ "\nGenerate.genFCall': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
396 genFromSizedWord :: BuiltinBuilder
397 genFromSizedWord = genNoInsts $ genExprArgs genFromSizedWord'
398 genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm]
399 genFromSizedWord' (Left res) f args@[arg] =
400 return [mkUncondAssign (Left res) arg]
401 -- let fname = varToString f
402 -- return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $
403 -- map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
404 genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
406 genResize :: BuiltinBuilder
407 genResize = genNoInsts $ genExprArgs $ genExprRes genResize'
408 genResize' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
409 genResize' (Left res) f [arg] = do {
410 ; let { ty = Var.varType res
411 ; (tycon, args) = Type.splitTyConApp ty
412 ; name = Name.getOccString (TyCon.tyConName tycon)
414 ; len <- case name of
415 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
416 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
417 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId resizeId))
418 [Nothing AST.:=>: AST.ADExpr arg, Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
420 genResize' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
422 genTimes :: BuiltinBuilder
423 genTimes = genNoInsts $ genExprArgs $ genExprRes genTimes'
424 genTimes' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
425 genTimes' (Left res) f [arg1,arg2] = do {
426 ; let { ty = Var.varType res
427 ; (tycon, args) = Type.splitTyConApp ty
428 ; name = Name.getOccString (TyCon.tyConName tycon)
430 ; len <- case name of
431 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
432 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
433 "RangedWord" -> do { ubound <- MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty)
434 ; let bitsize = floor (logBase 2 (fromInteger (toInteger ubound)))
437 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId resizeId))
438 [Nothing AST.:=>: AST.ADExpr (arg1 AST.:*: arg2), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
440 genTimes' (Right name) _ _ = error $ "\nGenerate.genTimes': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
442 -- FIXME: I'm calling genLitArgs which is very specific function,
443 -- which needs to be fixed as well
444 genFromInteger :: BuiltinBuilder
445 genFromInteger = genNoInsts $ genLitArgs $ genExprRes genFromInteger'
446 genFromInteger' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [Literal.Literal] -> TranslatorSession AST.Expr
447 genFromInteger' (Left res) f lits = do {
448 ; let { ty = Var.varType res
449 ; (tycon, args) = Type.splitTyConApp ty
450 ; name = Name.getOccString (TyCon.tyConName tycon)
452 ; len <- case name of
453 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
454 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
456 ; bound <- MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty)
457 ; return $ floor (logBase 2 (fromInteger (toInteger (bound)))) + 1
459 ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId ; "RangedWord" -> toUnsignedId
460 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname))
461 [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
465 genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
467 genSizedInt :: BuiltinBuilder
468 genSizedInt = genFromInteger
471 -- | Generate a Builder for the builtin datacon TFVec
472 genTFVec :: BuiltinBuilder
473 genTFVec (Left res) f [Left (CoreSyn.Let (CoreSyn.Rec letBinders) letRes)] = do {
474 -- Generate Assignments for all the binders
475 ; letAssigns <- mapM genBinderAssign letBinders
476 -- Generate assignments for the result (which might be another let binding)
477 ; (resBinders,resAssignments) <- genResAssign letRes
478 -- Get all the Assigned binders
479 ; let assignedBinders = Maybe.catMaybes (map fst letAssigns)
480 -- Make signal names for all the assigned binders
481 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) (assignedBinders ++ resBinders)
482 -- Assign all the signals to the resulting vector
483 ; let { vecsigns = mkAggregateSignal sigs
484 ; vecassign = mkUncondAssign (Left res) vecsigns
486 -- Generate all the signal declaration for the assigned binders
487 ; sig_dec_maybes <- mapM mkSigDec (assignedBinders ++ resBinders)
488 ; let { sig_decs = map (AST.BDISD) (Maybe.catMaybes $ sig_dec_maybes)
489 -- Setup the VHDL Block
490 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
491 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) sig_decs ((concat (map snd letAssigns)) ++ resAssignments ++ [vecassign])
493 -- Return the block statement coressponding to the TFVec literal
494 ; return $ [AST.CSBSm block]
497 genBinderAssign :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -> TranslatorSession (Maybe CoreSyn.CoreBndr, [AST.ConcSm])
498 -- For now we only translate applications
499 genBinderAssign (bndr, app@(CoreSyn.App _ _)) = do
500 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
501 let valargs = get_val_args (Var.varType f) args
502 apps <- genApplication (Left bndr) f (map Left valargs)
503 return (Just bndr, apps)
504 genBinderAssign _ = return (Nothing,[])
505 genResAssign :: CoreSyn.CoreExpr -> TranslatorSession ([CoreSyn.CoreBndr], [AST.ConcSm])
506 genResAssign app@(CoreSyn.App _ letexpr) = do
508 (CoreSyn.Let (CoreSyn.Rec letbndrs) letres) -> do
509 letapps <- mapM genBinderAssign letbndrs
510 let bndrs = Maybe.catMaybes (map fst letapps)
511 let app = (map snd letapps)
512 (vars, apps) <- genResAssign letres
513 return ((bndrs ++ vars),((concat app) ++ apps))
514 otherwise -> return ([],[])
515 genResAssign _ = return ([],[])
517 genTFVec (Left res) f [Left app@(CoreSyn.App _ _)] = do {
518 ; let { elems = reduceCoreListToHsList app
519 -- Make signal names for all the binders
520 ; binders = map (\expr -> case expr of
522 otherwise -> error $ "\nGenerate.genTFVec: Cannot generate TFVec: "
523 ++ show res ++ ", with elems:\n" ++ show elems ++ "\n" ++ pprString elems) elems
525 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) binders
526 -- Assign all the signals to the resulting vector
527 ; let { vecsigns = mkAggregateSignal sigs
528 ; vecassign = mkUncondAssign (Left res) vecsigns
529 -- Setup the VHDL Block
530 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
531 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) [] [vecassign]
533 -- Return the block statement coressponding to the TFVec literal
534 ; return $ [AST.CSBSm block]
537 genTFVec (Left name) _ [Left xs] = error $ "\nGenerate.genTFVec: Cannot generate TFVec: " ++ show name ++ ", with elems:\n" ++ show xs ++ "\n" ++ pprString xs
539 genTFVec (Right name) _ _ = error $ "\nGenerate.genTFVec: Cannot generate TFVec assigned to VHDLName: " ++ show name
541 -- | Generate a generate statement for the builtin function "map"
542 genMap :: BuiltinBuilder
543 genMap (Left res) f [Left mapped_f, Left (CoreSyn.Var arg)] = do {
544 -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL
545 -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since
546 -- we must index it (which we couldn't if it was a VHDL Expr, since only
547 -- VHDLNames can be indexed).
548 -- Setup the generate scheme
549 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
550 -- TODO: Use something better than varToString
551 ; let { label = mkVHDLExtId ("mapVector" ++ (varToString res))
552 ; n_id = mkVHDLBasicId "n"
553 ; n_expr = idToVHDLExpr n_id
554 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
555 ; genScheme = AST.ForGn n_id range
556 -- Create the content of the generate statement: Applying the mapped_f to
557 -- each of the elements in arg, storing to each element in res
558 ; resname = mkIndexedName (varToVHDLName res) n_expr
559 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
560 ; (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f
561 ; valargs = get_val_args (Var.varType real_f) already_mapped_args
563 ; (app_concsms, used) <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr])
564 -- Return the generate statement
565 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
568 genMap' (Right name) _ _ = error $ "\nGenerate.genMap': Cannot generate map function call assigned to a VHDLName: " ++ show name
570 genZipWith :: BuiltinBuilder
571 genZipWith = genVarArgs genZipWith'
572 genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
573 genZipWith' (Left res) f args@[zipped_f, arg1, arg2] = do {
574 -- Setup the generate scheme
575 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
576 -- TODO: Use something better than varToString
577 ; let { label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
578 ; n_id = mkVHDLBasicId "n"
579 ; n_expr = idToVHDLExpr n_id
580 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
581 ; genScheme = AST.ForGn n_id range
582 -- Create the content of the generate statement: Applying the zipped_f to
583 -- each of the elements in arg1 and arg2, storing to each element in res
584 ; resname = mkIndexedName (varToVHDLName res) n_expr
585 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
586 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
588 ; (app_concsms, used) <- genApplication (Right resname) zipped_f [Right argexpr1, Right argexpr2]
589 -- Return the generate functions
590 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
593 genFoldl :: BuiltinBuilder
594 genFoldl = genFold True
596 genFoldr :: BuiltinBuilder
597 genFoldr = genFold False
599 genFold :: Bool -> BuiltinBuilder
600 genFold left = genVarArgs (genFold' left)
602 genFold' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
603 genFold' left res f args@[folded_f , start ,vec]= do
604 len <- MonadState.lift tsType $ tfp_to_int (tfvec_len_ty (Var.varType vec))
605 genFold'' len left res f args
607 genFold'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
608 -- Special case for an empty input vector, just assign start to res
609 genFold'' len left (Left res) _ [_, start, vec] | len == 0 = do
610 arg <- MonadState.lift tsType $ varToVHDLExpr start
611 return ([mkUncondAssign (Left res) arg], [])
613 genFold'' len left (Left res) f [folded_f, start, vec] = do
615 --len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
616 -- An expression for len-1
617 let len_min_expr = (AST.PrimLit $ show (len-1))
618 -- evec is (TFVec n), so it still needs an element type
619 let (nvec, _) = Type.splitAppTy (Var.varType vec)
620 -- Put the type of the start value in nvec, this will be the type of our
622 let tmp_ty = Type.mkAppTy nvec (Var.varType start)
623 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
624 -- TODO: Handle Nothing
625 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdlTy error_msg tmp_ty
626 -- Setup the generate scheme
627 let gen_label = mkVHDLExtId ("foldlVector" ++ (varToString vec))
628 let block_label = mkVHDLExtId ("foldlVector" ++ (varToString res))
629 let gen_range = if left then AST.ToRange (AST.PrimLit "0") len_min_expr
630 else AST.DownRange len_min_expr (AST.PrimLit "0")
631 let gen_scheme = AST.ForGn n_id gen_range
632 -- Make the intermediate vector
633 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
634 -- Create the generate statement
635 cells' <- sequence [genFirstCell, genOtherCell]
636 let (cells, useds) = unzip cells'
637 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
638 -- Assign tmp[len-1] or tmp[0] to res
639 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr (if left then
640 (mkIndexedName tmp_name (AST.PrimLit $ show (len-1))) else
641 (mkIndexedName tmp_name (AST.PrimLit "0")))
642 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
643 return ([AST.CSBSm block], concat useds)
645 -- An id for the counter
646 n_id = mkVHDLBasicId "n"
647 n_cur = idToVHDLExpr n_id
648 -- An expression for previous n
649 n_prev = if left then (n_cur AST.:-: (AST.PrimLit "1"))
650 else (n_cur AST.:+: (AST.PrimLit "1"))
651 -- An id for the tmp result vector
652 tmp_id = mkVHDLBasicId "tmp"
653 tmp_name = AST.NSimple tmp_id
654 -- Generate parts of the fold
655 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
657 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
658 let cond_label = mkVHDLExtId "firstcell"
659 -- if n == 0 or n == len-1
660 let cond_scheme = AST.IfGn $ n_cur AST.:=: (if left then (AST.PrimLit "0")
661 else (AST.PrimLit $ show (len-1)))
662 -- Output to tmp[current n]
663 let resname = mkIndexedName tmp_name n_cur
665 argexpr1 <- MonadState.lift tsType $ varToVHDLExpr start
666 -- Input from vec[current n]
667 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
668 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
669 [Right argexpr1, Right argexpr2]
671 [Right argexpr2, Right argexpr1]
673 -- Return the conditional generate part
674 return (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
677 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
678 let cond_label = mkVHDLExtId "othercell"
679 -- if n > 0 or n < len-1
680 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (if left then (AST.PrimLit "0")
681 else (AST.PrimLit $ show (len-1)))
682 -- Output to tmp[current n]
683 let resname = mkIndexedName tmp_name n_cur
684 -- Input from tmp[previous n]
685 let argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
686 -- Input from vec[current n]
687 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
688 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
689 [Right argexpr1, Right argexpr2]
691 [Right argexpr2, Right argexpr1]
693 -- Return the conditional generate part
694 return (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
696 -- | Generate a generate statement for the builtin function "zip"
697 genZip :: BuiltinBuilder
698 genZip = genNoInsts $ genVarArgs genZip'
699 genZip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
700 genZip' (Left res) f args@[arg1, arg2] = do {
701 -- Setup the generate scheme
702 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
703 -- TODO: Use something better than varToString
704 ; let { label = mkVHDLExtId ("zipVector" ++ (varToString res))
705 ; n_id = mkVHDLBasicId "n"
706 ; n_expr = idToVHDLExpr n_id
707 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
708 ; genScheme = AST.ForGn n_id range
709 ; resname' = mkIndexedName (varToVHDLName res) n_expr
710 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
711 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
713 ; labels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType res))
714 ; let { resnameA = mkSelectedName resname' (labels!!0)
715 ; resnameB = mkSelectedName resname' (labels!!1)
716 ; resA_assign = mkUncondAssign (Right resnameA) argexpr1
717 ; resB_assign = mkUncondAssign (Right resnameB) argexpr2
719 -- Return the generate functions
720 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
723 -- | Generate a generate statement for the builtin function "fst"
724 genFst :: BuiltinBuilder
725 genFst = genNoInsts $ genVarArgs genFst'
726 genFst' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
727 genFst' (Left res) f args@[arg] = do {
728 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg)
729 ; let { argexpr' = varToVHDLName arg
730 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!0)
731 ; assign = mkUncondAssign (Left res) argexprA
733 -- Return the generate functions
737 -- | Generate a generate statement for the builtin function "snd"
738 genSnd :: BuiltinBuilder
739 genSnd = genNoInsts $ genVarArgs genSnd'
740 genSnd' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
741 genSnd' (Left res) f args@[arg] = do {
742 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg)
743 ; let { argexpr' = varToVHDLName arg
744 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!1)
745 ; assign = mkUncondAssign (Left res) argexprB
747 -- Return the generate functions
751 -- | Generate a generate statement for the builtin function "unzip"
752 genUnzip :: BuiltinBuilder
753 genUnzip = genNoInsts $ genVarArgs genUnzip'
754 genUnzip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
755 genUnzip' (Left res) f args@[arg] = do
756 let error_msg = "\nGenerate.genUnzip: Cannot generate unzip call: " ++ pprString res ++ " = " ++ pprString f ++ " " ++ pprString arg
757 htype <- MonadState.lift tsType $ mkHType error_msg (Var.varType arg)
758 -- Prepare a unconditional assignment, for the case when either part
759 -- of the unzip is a state variable, which will disappear in the
760 -- resulting VHDL, making the the unzip no longer required.
762 -- A normal vector containing two-tuples
763 VecType _ (AggrType _ [_, _]) -> do {
764 -- Setup the generate scheme
765 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
766 -- TODO: Use something better than varToString
767 ; let { label = mkVHDLExtId ("unzipVector" ++ (varToString res))
768 ; n_id = mkVHDLBasicId "n"
769 ; n_expr = idToVHDLExpr n_id
770 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
771 ; genScheme = AST.ForGn n_id range
772 ; resname' = varToVHDLName res
773 ; argexpr' = mkIndexedName (varToVHDLName arg) n_expr
775 ; reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
776 ; arglabels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType arg))
777 ; let { resnameA = mkIndexedName (mkSelectedName resname' (reslabels!!0)) n_expr
778 ; resnameB = mkIndexedName (mkSelectedName resname' (reslabels!!1)) n_expr
779 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!0)
780 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!1)
781 ; resA_assign = mkUncondAssign (Right resnameA) argexprA
782 ; resB_assign = mkUncondAssign (Right resnameB) argexprB
784 -- Return the generate functions
785 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
787 -- Both elements of the tuple were state, so they've disappeared. No
788 -- need to do anything
789 VecType _ (AggrType _ []) -> return []
790 -- A vector containing aggregates with more than two elements?
791 VecType _ (AggrType _ _) -> error $ "Unzipping a value that is not a vector of two-tuples? Value: " ++ pprString arg ++ "\nType: " ++ pprString (Var.varType arg)
792 -- One of the elements of the tuple was state, so there won't be a
793 -- tuple (record) in the VHDL output. We can just do a plain
796 argexpr <- MonadState.lift tsType $ varToVHDLExpr arg
797 return [mkUncondAssign (Left res) argexpr]
798 _ -> error $ "Unzipping a value that is not a vector? Value: " ++ pprString arg ++ "\nType: " ++ pprString (Var.varType arg) ++ "\nhtype: " ++ show htype
800 genCopy :: BuiltinBuilder
801 genCopy = genNoInsts $ genVarArgs genCopy'
802 genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
803 genCopy' (Left res) f args@[arg] =
805 resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others)
806 (AST.PrimName (varToVHDLName arg))]
807 out_assign = mkUncondAssign (Left res) resExpr
811 genConcat :: BuiltinBuilder
812 genConcat = genNoInsts $ genVarArgs genConcat'
813 genConcat' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
814 genConcat' (Left res) f args@[arg] = do {
815 -- Setup the generate scheme
816 ; len1 <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
817 ; let (_, nvec) = Type.splitAppTy (Var.varType arg)
818 ; len2 <- MonadState.lift tsType $ tfp_to_int $ tfvec_len_ty nvec
819 -- TODO: Use something better than varToString
820 ; let { label = mkVHDLExtId ("concatVector" ++ (varToString res))
821 ; n_id = mkVHDLBasicId "n"
822 ; n_expr = idToVHDLExpr n_id
823 ; fromRange = n_expr AST.:*: (AST.PrimLit $ show len2)
824 ; genScheme = AST.ForGn n_id range
825 -- Create the content of the generate statement: Applying the mapped_f to
826 -- each of the elements in arg, storing to each element in res
827 ; toRange = (n_expr AST.:*: (AST.PrimLit $ show len2)) AST.:+: (AST.PrimLit $ show (len2-1))
828 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len1-1))
829 ; resname = vecSlice fromRange toRange
830 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
831 ; out_assign = mkUncondAssign (Right resname) argexpr
833 -- Return the generate statement
834 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [out_assign]]
837 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
838 (AST.ToRange init last))
840 genIteraten :: BuiltinBuilder
841 genIteraten dst f args = genIterate dst f (tail args)
843 genIterate :: BuiltinBuilder
844 genIterate = genIterateOrGenerate True
846 genGeneraten :: BuiltinBuilder
847 genGeneraten dst f args = genGenerate dst f (tail args)
849 genGenerate :: BuiltinBuilder
850 genGenerate = genIterateOrGenerate False
852 genIterateOrGenerate :: Bool -> BuiltinBuilder
853 genIterateOrGenerate iter = genVarArgs (genIterateOrGenerate' iter)
855 genIterateOrGenerate' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
856 genIterateOrGenerate' iter (Left res) f args = do
857 len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
858 genIterateOrGenerate'' len iter (Left res) f args
860 genIterateOrGenerate'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
861 -- Special case for an empty input vector, just assign start to res
862 genIterateOrGenerate'' len iter (Left res) _ [app_f, start] | len == 0 = return ([mkUncondAssign (Left res) (AST.PrimLit "\"\"")], [])
864 genIterateOrGenerate'' len iter (Left res) f [app_f, start] = do
866 -- len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
867 -- An expression for len-1
868 let len_min_expr = (AST.PrimLit $ show (len-1))
869 -- -- evec is (TFVec n), so it still needs an element type
870 -- let (nvec, _) = splitAppTy (Var.varType vec)
871 -- -- Put the type of the start value in nvec, this will be the type of our
872 -- -- temporary vector
873 let tmp_ty = Var.varType res
874 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
875 -- TODO: Handle Nothing
876 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdlTy error_msg tmp_ty
877 -- Setup the generate scheme
878 let gen_label = mkVHDLExtId ("iterateVector" ++ (varToString start))
879 let block_label = mkVHDLExtId ("iterateVector" ++ (varToString res))
880 let gen_range = AST.ToRange (AST.PrimLit "0") len_min_expr
881 let gen_scheme = AST.ForGn n_id gen_range
882 -- Make the intermediate vector
883 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
884 -- Create the generate statement
885 cells' <- sequence [genFirstCell, genOtherCell]
886 let (cells, useds) = unzip cells'
887 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
888 -- Assign tmp[len-1] or tmp[0] to res
889 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr tmp_name
890 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
891 return ([AST.CSBSm block], concat useds)
893 -- An id for the counter
894 n_id = mkVHDLBasicId "n"
895 n_cur = idToVHDLExpr n_id
896 -- An expression for previous n
897 n_prev = n_cur AST.:-: (AST.PrimLit "1")
898 -- An id for the tmp result vector
899 tmp_id = mkVHDLBasicId "tmp"
900 tmp_name = AST.NSimple tmp_id
901 -- Generate parts of the fold
902 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
904 let cond_label = mkVHDLExtId "firstcell"
905 -- if n == 0 or n == len-1
906 let cond_scheme = AST.IfGn $ n_cur AST.:=: (AST.PrimLit "0")
907 -- Output to tmp[current n]
908 let resname = mkIndexedName tmp_name n_cur
910 argexpr <- MonadState.lift tsType $ varToVHDLExpr start
911 let startassign = mkUncondAssign (Right resname) argexpr
912 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
913 -- Return the conditional generate part
914 let gensm = AST.GenerateSm cond_label cond_scheme [] (if iter then
922 let cond_label = mkVHDLExtId "othercell"
923 -- if n > 0 or n < len-1
924 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (AST.PrimLit "0")
925 -- Output to tmp[current n]
926 let resname = mkIndexedName tmp_name n_cur
927 -- Input from tmp[previous n]
928 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
929 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
930 -- Return the conditional generate part
931 return (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
933 genBlockRAM :: BuiltinBuilder
934 genBlockRAM = genNoInsts $ genExprArgs genBlockRAM'
936 genBlockRAM' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm]
937 genBlockRAM' (Left res) f args@[data_in,rdaddr,wraddr,wrenable] = do
939 let (tup,data_out) = Type.splitAppTy (Var.varType res)
940 let (tup',ramvec) = Type.splitAppTy tup
941 let Just realram = Type.coreView ramvec
942 let Just (tycon, types) = Type.splitTyConApp_maybe realram
943 Just ram_vhdl_ty <- MonadState.lift tsType $ vhdlTy "wtf" (head types)
944 -- Make the intermediate vector
945 let ram_dec = AST.BDISD $ AST.SigDec ram_id ram_vhdl_ty Nothing
946 -- Get the data_out name
947 -- reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
948 let resname = varToVHDLName res
949 -- let resname = mkSelectedName resname' (reslabels!!0)
950 let rdaddr_int = genExprFCall (mkVHDLBasicId toIntegerId) rdaddr
951 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName (AST.NSimple ram_id) rdaddr_int
952 let assign = mkUncondAssign (Right resname) argexpr
953 let block_label = mkVHDLExtId ("blockRAM" ++ (varToString res))
954 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [ram_dec] [assign, mkUpdateProcSm]
955 return [AST.CSBSm block]
957 ram_id = mkVHDLBasicId "ram"
958 mkUpdateProcSm :: AST.ConcSm
959 mkUpdateProcSm = AST.CSPSm $ AST.ProcSm proclabel [clockId] [statement]
961 proclabel = mkVHDLBasicId "updateRAM"
962 rising_edge = mkVHDLBasicId "rising_edge"
963 wraddr_int = genExprFCall (mkVHDLBasicId toIntegerId) wraddr
964 ramloc = mkIndexedName (AST.NSimple ram_id) wraddr_int
965 wform = AST.Wform [AST.WformElem data_in Nothing]
966 ramassign = AST.SigAssign ramloc wform
967 rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
968 statement = AST.IfSm (AST.And rising_edge_clk wrenable) [ramassign] [] Nothing
970 genSplit :: BuiltinBuilder
971 genSplit = genNoInsts $ genVarArgs genSplit'
973 genSplit' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
974 genSplit' (Left res) f args@[vecIn] = do {
975 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
976 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vecIn
977 ; let { block_label = mkVHDLExtId ("split" ++ (varToString vecIn))
978 ; halflen = round ((fromIntegral len) / 2)
979 ; rangeL = vecSlice (AST.PrimLit "0") (AST.PrimLit $ show (halflen - 1))
980 ; rangeR = vecSlice (AST.PrimLit $ show halflen) (AST.PrimLit $ show (len - 1))
981 ; resname = varToVHDLName res
982 ; resnameL = mkSelectedName resname (labels!!0)
983 ; resnameR = mkSelectedName resname (labels!!1)
984 ; argexprL = vhdlNameToVHDLExpr rangeL
985 ; argexprR = vhdlNameToVHDLExpr rangeR
986 ; out_assignL = mkUncondAssign (Right resnameL) argexprL
987 ; out_assignR = mkUncondAssign (Right resnameR) argexprR
988 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) [] [out_assignL, out_assignR]
990 ; return [AST.CSBSm block]
993 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
994 (AST.ToRange init last))
995 -----------------------------------------------------------------------------
996 -- Function to generate VHDL for applications
997 -----------------------------------------------------------------------------
999 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
1000 -> CoreSyn.CoreBndr -- ^ The function to apply
1001 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
1002 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
1003 -- ^ The corresponding VHDL concurrent statements and entities
1005 genApplication dst f args =
1006 if Var.isGlobalId f then
1007 case Var.idDetails f of
1008 IdInfo.DataConWorkId dc -> case dst of
1009 -- It's a datacon. Create a record from its arguments.
1011 -- We have the bndr, so we can get at the type
1012 htype <- MonadState.lift tsType $ mkHTypeEither (Var.varType bndr)
1013 let argsNostate = filter (\x -> not (either hasStateType (\x -> False) x)) args
1016 [arg'] <- argsToVHDLExprs [arg]
1017 return ([mkUncondAssign dst arg'], [])
1020 Right (AggrType _ _) -> do
1021 labels <- MonadState.lift tsType $ getFieldLabels (Var.varType bndr)
1022 args' <- argsToVHDLExprs argsNostate
1023 return (zipWith mkassign labels args', [])
1025 mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
1026 mkassign label arg =
1027 let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
1028 mkUncondAssign (Right sel_name) arg
1029 _ -> do -- error $ "DIE!"
1030 args' <- argsToVHDLExprs argsNostate
1031 return ([mkUncondAssign dst (head args')], [])
1032 Right _ -> error "\nGenerate.genApplication(DataConWorkId): Can't generate dataconstructor application without an original binder"
1033 IdInfo.DataConWrapId dc -> case dst of
1034 -- It's a datacon. Create a record from its arguments.
1036 case (Map.lookup (varToString f) globalNameTable) of
1037 Just (arg_count, builder) ->
1038 if length args == arg_count then
1041 error $ "\nGenerate.genApplication(DataConWrapId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
1042 Nothing -> error $ "\nGenerate.genApplication(DataConWrapId): Can't generate dataconwrapper: " ++ (show dc)
1043 Right _ -> error "\nGenerate.genApplication(DataConWrapId): Can't generate dataconwrapper application without an original binder"
1045 -- It's a global value imported from elsewhere. These can be builtin
1046 -- functions. Look up the function name in the name table and execute
1047 -- the associated builder if there is any and the argument count matches
1048 -- (this should always be the case if it typechecks, but just to be
1050 case (Map.lookup (varToString f) globalNameTable) of
1051 Just (arg_count, builder) ->
1052 if length args == arg_count then
1055 error $ "\nGenerate.genApplication(VanillaId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
1057 top <- isTopLevelBinder f
1060 -- Local binder that references a top level binding. Generate a
1061 -- component instantiation.
1062 signature <- getEntity f
1063 args' <- argsToVHDLExprs args
1064 let entity_id = ent_id signature
1065 -- TODO: Using show here isn't really pretty, but we'll need some
1066 -- unique-ish value...
1067 let label = "comp_ins_" ++ (either show prettyShow) dst
1068 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
1069 return ([mkComponentInst label entity_id portmaps], [f])
1071 -- Not a top level binder, so this must be a local variable reference.
1072 -- It should have a representable type (and thus, no arguments) and a
1073 -- signal should be generated for it. Just generate an unconditional
1075 -- FIXME : I DONT KNOW IF THE ABOVE COMMENT HOLDS HERE, SO FOR NOW JUST ERROR!
1076 -- f' <- MonadState.lift tsType $ varToVHDLExpr f
1077 -- return $ ([mkUncondAssign dst f'], [])
1078 do errtype <- case dst of
1080 htype <- MonadState.lift tsType $ mkHTypeEither (Var.varType bndr)
1082 Right vhd -> return $ show vhd
1083 error ("\nGenerate.genApplication(VanillaId): Using function from another module that is not a known builtin: " ++ (pprString f) ++ "::" ++ errtype)
1084 IdInfo.ClassOpId cls ->
1085 -- FIXME: Not looking for what instance this class op is called for
1086 -- Is quite stupid of course.
1087 case (Map.lookup (varToString f) globalNameTable) of
1088 Just (arg_count, builder) ->
1089 if length args == arg_count then
1092 error $ "\nGenerate.genApplication(ClassOpId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
1093 Nothing -> error $ "\nGenerate.genApplication(ClassOpId): Using function from another module that is not a known builtin: " ++ pprString f
1094 details -> error $ "\nGenerate.genApplication: Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
1096 top <- isTopLevelBinder f
1099 -- Local binder that references a top level binding. Generate a
1100 -- component instantiation.
1101 signature <- getEntity f
1102 args' <- argsToVHDLExprs args
1103 let entity_id = ent_id signature
1104 -- TODO: Using show here isn't really pretty, but we'll need some
1105 -- unique-ish value...
1106 let label = "comp_ins_" ++ (either (prettyShow . varToVHDLName) prettyShow) dst
1107 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
1108 return ([mkComponentInst label entity_id portmaps], [f])
1110 -- Not a top level binder, so this must be a local variable reference.
1111 -- It should have a representable type (and thus, no arguments) and a
1112 -- signal should be generated for it. Just generate an unconditional
1114 do f' <- MonadState.lift tsType $ varToVHDLExpr f
1115 return ([mkUncondAssign dst f'], [])
1117 -----------------------------------------------------------------------------
1118 -- Functions to generate functions dealing with vectors.
1119 -----------------------------------------------------------------------------
1121 -- Returns the VHDLId of the vector function with the given name for the given
1122 -- element type. Generates -- this function if needed.
1123 vectorFunId :: Type.Type -> String -> TypeSession AST.VHDLId
1124 vectorFunId el_ty fname = do
1125 let error_msg = "\nGenerate.vectorFunId: Can not construct vector function for element: " ++ pprString el_ty
1126 -- TODO: Handle the Nothing case?
1127 elemTM_maybe <- vhdlTy error_msg el_ty
1128 let elemTM = Maybe.fromMaybe
1129 (error $ "\nGenerate.vectorFunId: Cannot generate vector function \"" ++ fname ++ "\" for the empty type \"" ++ (pprString el_ty) ++ "\"")
1131 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
1132 -- the VHDLState or something.
1133 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
1134 typefuns <- MonadState.get tsTypeFuns
1135 el_htype <- mkHType error_msg el_ty
1136 case Map.lookup (UVecType el_htype, fname) typefuns of
1137 -- Function already generated, just return it
1138 Just (id, _) -> return id
1139 -- Function not generated yet, generate it
1141 let functions = genUnconsVectorFuns elemTM vectorTM
1142 case lookup fname functions of
1144 MonadState.modify tsTypeFuns $ Map.insert (UVecType el_htype, fname) (function_id, (fst body))
1145 mapM_ (vectorFunId el_ty) (snd body)
1147 Nothing -> error $ "\nGenerate.vectorFunId: I don't know how to generate vector function " ++ fname
1149 function_id = mkVHDLExtId fname
1151 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
1152 -> AST.TypeMark -- ^ type of the vector
1153 -> [(String, (AST.SubProgBody, [String]))]
1154 genUnconsVectorFuns elemTM vectorTM =
1155 [ (exId, (AST.SubProgBody exSpec [] [exExpr],[]))
1156 , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr1,replaceExpr2,replaceRet],[]))
1157 , (lastId, (AST.SubProgBody lastSpec [] [lastExpr],[]))
1158 , (initId, (AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet],[]))
1159 , (minimumId, (AST.SubProgBody minimumSpec [] [minimumExpr],[]))
1160 , (takeId, (AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet],[minimumId]))
1161 , (dropId, (AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet],[]))
1162 , (plusgtId, (AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet],[]))
1163 , (emptyId, (AST.SubProgBody emptySpec [AST.SPVD emptyVar] [emptyExpr],[]))
1164 , (singletonId, (AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet],[]))
1165 , (copynId, (AST.SubProgBody copynSpec [AST.SPVD copynVar] [copynExpr],[]))
1166 , (selId, (AST.SubProgBody selSpec [AST.SPVD selVar] [selFor, selRet],[]))
1167 , (ltplusId, (AST.SubProgBody ltplusSpec [AST.SPVD ltplusVar] [ltplusExpr, ltplusRet],[]))
1168 , (plusplusId, (AST.SubProgBody plusplusSpec [AST.SPVD plusplusVar] [plusplusExpr, plusplusRet],[]))
1169 , (lengthTId, (AST.SubProgBody lengthTSpec [] [lengthTExpr],[]))
1170 , (shiftlId, (AST.SubProgBody shiftlSpec [AST.SPVD shiftlVar] [shiftlExpr, shiftlRet], [initId]))
1171 , (shiftrId, (AST.SubProgBody shiftrSpec [AST.SPVD shiftrVar] [shiftrExpr, shiftrRet], [tailId]))
1172 , (nullId, (AST.SubProgBody nullSpec [] [nullExpr], []))
1173 , (rotlId, (AST.SubProgBody rotlSpec [AST.SPVD rotlVar] [rotlExpr, rotlRet], [nullId, lastId, initId]))
1174 , (rotrId, (AST.SubProgBody rotrSpec [AST.SPVD rotrVar] [rotrExpr, rotrRet], [nullId, tailId, headId]))
1175 , (reverseId, (AST.SubProgBody reverseSpec [AST.SPVD reverseVar] [reverseFor, reverseRet], []))
1178 ixPar = AST.unsafeVHDLBasicId "ix"
1179 vecPar = AST.unsafeVHDLBasicId "vec"
1180 vec1Par = AST.unsafeVHDLBasicId "vec1"
1181 vec2Par = AST.unsafeVHDLBasicId "vec2"
1182 nPar = AST.unsafeVHDLBasicId "n"
1183 leftPar = AST.unsafeVHDLBasicId "nLeft"
1184 rightPar = AST.unsafeVHDLBasicId "nRight"
1185 iId = AST.unsafeVHDLBasicId "i"
1187 aPar = AST.unsafeVHDLBasicId "a"
1188 fPar = AST.unsafeVHDLBasicId "f"
1189 sPar = AST.unsafeVHDLBasicId "s"
1190 resId = AST.unsafeVHDLBasicId "res"
1191 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
1192 AST.IfaceVarDec ixPar unsignedTM] elemTM
1193 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
1194 (AST.IndexedName (AST.NSimple vecPar) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple ixPar)]))
1195 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
1196 , AST.IfaceVarDec iPar unsignedTM
1197 , AST.IfaceVarDec aPar elemTM
1199 -- variable res : fsvec_x (0 to vec'length-1);
1202 (AST.SubtypeIn vectorTM
1203 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1204 [AST.ToRange (AST.PrimLit "0")
1205 (AST.PrimName (AST.NAttribute $
1206 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1207 (AST.PrimLit "1")) ]))
1209 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
1210 replaceExpr1 = AST.NSimple resId AST.:= AST.PrimName (AST.NSimple vecPar)
1211 replaceExpr2 = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple iPar)]) AST.:= AST.PrimName (AST.NSimple aPar)
1212 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1213 vecSlice init last = AST.PrimName (AST.NSlice
1215 (AST.NSimple vecPar)
1216 (AST.ToRange init last)))
1217 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
1218 -- return vec(vec'length-1);
1219 lastExpr = AST.ReturnSm (Just (AST.PrimName $ AST.NIndexed (AST.IndexedName
1220 (AST.NSimple vecPar)
1221 [AST.PrimName (AST.NAttribute $
1222 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1223 AST.:-: AST.PrimLit "1"])))
1224 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1225 -- variable res : fsvec_x (0 to vec'length-2);
1228 (AST.SubtypeIn vectorTM
1229 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1230 [AST.ToRange (AST.PrimLit "0")
1231 (AST.PrimName (AST.NAttribute $
1232 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1233 (AST.PrimLit "2")) ]))
1235 -- resAST.:= vec(0 to vec'length-2)
1236 initExpr = AST.NSimple resId AST.:= (vecSlice
1238 (AST.PrimName (AST.NAttribute $
1239 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1240 AST.:-: AST.PrimLit "2"))
1241 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1242 minimumSpec = AST.Function (mkVHDLExtId minimumId) [AST.IfaceVarDec leftPar naturalTM,
1243 AST.IfaceVarDec rightPar naturalTM ] naturalTM
1244 minimumExpr = AST.IfSm ((AST.PrimName $ AST.NSimple leftPar) AST.:<: (AST.PrimName $ AST.NSimple rightPar))
1245 [AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple leftPar)]
1247 (Just $ AST.Else [minimumExprRet])
1248 where minimumExprRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple rightPar)
1249 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
1250 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1251 -- variable res : fsvec_x (0 to (minimum (n,vec'length))-1);
1252 minLength = AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId minimumId))
1253 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple nPar)
1254 ,Nothing AST.:=>: AST.ADExpr (AST.PrimName (AST.NAttribute $
1255 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]
1258 (AST.SubtypeIn vectorTM
1259 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1260 [AST.ToRange (AST.PrimLit "0")
1262 (AST.PrimLit "1")) ]))
1264 -- res AST.:= vec(0 to n-1)
1265 takeExpr = AST.NSimple resId AST.:=
1266 (vecSlice (AST.PrimLit "0")
1267 (minLength AST.:-: AST.PrimLit "1"))
1268 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1269 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
1270 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1271 -- variable res : fsvec_x (0 to vec'length-n-1);
1274 (AST.SubtypeIn vectorTM
1275 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1276 [AST.ToRange (AST.PrimLit "0")
1277 (AST.PrimName (AST.NAttribute $
1278 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1279 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
1281 -- res AST.:= vec(n to vec'length-1)
1282 dropExpr = AST.NSimple resId AST.:= (vecSlice
1283 (AST.PrimName $ AST.NSimple nPar)
1284 (AST.PrimName (AST.NAttribute $
1285 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1286 AST.:-: AST.PrimLit "1"))
1287 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1288 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
1289 AST.IfaceVarDec vecPar vectorTM] vectorTM
1290 -- variable res : fsvec_x (0 to vec'length);
1293 (AST.SubtypeIn vectorTM
1294 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1295 [AST.ToRange (AST.PrimLit "0")
1296 (AST.PrimName (AST.NAttribute $
1297 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1299 plusgtExpr = AST.NSimple resId AST.:=
1300 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
1301 (AST.PrimName $ AST.NSimple vecPar))
1302 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1303 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
1306 (AST.SubtypeIn vectorTM
1307 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1308 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "-1")]))
1310 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1311 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
1313 -- variable res : fsvec_x (0 to 0) := (others => a);
1316 (AST.SubtypeIn vectorTM
1317 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1318 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
1319 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1320 (AST.PrimName $ AST.NSimple aPar)])
1321 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1322 copynSpec = AST.Function (mkVHDLExtId copynId) [AST.IfaceVarDec nPar naturalTM,
1323 AST.IfaceVarDec aPar elemTM ] vectorTM
1324 -- variable res : fsvec_x (0 to n-1) := (others => a);
1327 (AST.SubtypeIn vectorTM
1328 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1329 [AST.ToRange (AST.PrimLit "0")
1330 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1331 (AST.PrimLit "1")) ]))
1332 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1333 (AST.PrimName $ AST.NSimple aPar)])
1335 copynExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1336 selSpec = AST.Function (mkVHDLExtId selId) [AST.IfaceVarDec fPar naturalTM,
1337 AST.IfaceVarDec sPar naturalTM,
1338 AST.IfaceVarDec nPar naturalTM,
1339 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1340 -- variable res : fsvec_x (0 to n-1);
1343 (AST.SubtypeIn vectorTM
1344 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1345 [AST.ToRange (AST.PrimLit "0")
1346 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1347 (AST.PrimLit "1")) ])
1350 -- for i res'range loop
1351 -- res(i) := vec(f+i*s);
1353 selFor = AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple rangeId) Nothing) [selAssign]
1354 -- res(i) := vec(f+i*s);
1355 selAssign = let origExp = AST.PrimName (AST.NSimple fPar) AST.:+:
1356 (AST.PrimName (AST.NSimple iId) AST.:*:
1357 AST.PrimName (AST.NSimple sPar)) in
1358 AST.NIndexed (AST.IndexedName (AST.NSimple resId) [AST.PrimName (AST.NSimple iId)]) AST.:=
1359 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [origExp]))
1361 selRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1362 ltplusSpec = AST.Function (mkVHDLExtId ltplusId) [AST.IfaceVarDec vecPar vectorTM,
1363 AST.IfaceVarDec aPar elemTM] vectorTM
1364 -- variable res : fsvec_x (0 to vec'length);
1367 (AST.SubtypeIn vectorTM
1368 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1369 [AST.ToRange (AST.PrimLit "0")
1370 (AST.PrimName (AST.NAttribute $
1371 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1373 ltplusExpr = AST.NSimple resId AST.:=
1374 ((AST.PrimName $ AST.NSimple vecPar) AST.:&:
1375 (AST.PrimName $ AST.NSimple aPar))
1376 ltplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1377 plusplusSpec = AST.Function (mkVHDLExtId plusplusId) [AST.IfaceVarDec vec1Par vectorTM,
1378 AST.IfaceVarDec vec2Par vectorTM]
1380 -- variable res : fsvec_x (0 to vec1'length + vec2'length -1);
1383 (AST.SubtypeIn vectorTM
1384 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1385 [AST.ToRange (AST.PrimLit "0")
1386 (AST.PrimName (AST.NAttribute $
1387 AST.AttribName (AST.NSimple vec1Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:+:
1388 AST.PrimName (AST.NAttribute $
1389 AST.AttribName (AST.NSimple vec2Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1392 plusplusExpr = AST.NSimple resId AST.:=
1393 ((AST.PrimName $ AST.NSimple vec1Par) AST.:&:
1394 (AST.PrimName $ AST.NSimple vec2Par))
1395 plusplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1396 lengthTSpec = AST.Function (mkVHDLExtId lengthTId) [AST.IfaceVarDec vecPar vectorTM] naturalTM
1397 lengthTExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NAttribute $
1398 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))
1399 shiftlSpec = AST.Function (mkVHDLExtId shiftlId) [AST.IfaceVarDec vecPar vectorTM,
1400 AST.IfaceVarDec aPar elemTM ] vectorTM
1401 -- variable res : fsvec_x (0 to vec'length-1);
1404 (AST.SubtypeIn vectorTM
1405 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1406 [AST.ToRange (AST.PrimLit "0")
1407 (AST.PrimName (AST.NAttribute $
1408 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1409 (AST.PrimLit "1")) ]))
1411 -- res := a & init(vec)
1412 shiftlExpr = AST.NSimple resId AST.:=
1413 (AST.PrimName (AST.NSimple aPar) AST.:&:
1414 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1415 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1416 shiftlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1417 shiftrSpec = AST.Function (mkVHDLExtId shiftrId) [AST.IfaceVarDec vecPar vectorTM,
1418 AST.IfaceVarDec aPar elemTM ] vectorTM
1419 -- variable res : fsvec_x (0 to vec'length-1);
1422 (AST.SubtypeIn vectorTM
1423 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1424 [AST.ToRange (AST.PrimLit "0")
1425 (AST.PrimName (AST.NAttribute $
1426 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1427 (AST.PrimLit "1")) ]))
1429 -- res := tail(vec) & a
1430 shiftrExpr = AST.NSimple resId AST.:=
1431 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1432 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1433 (AST.PrimName (AST.NSimple aPar)))
1435 shiftrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1436 nullSpec = AST.Function (mkVHDLExtId nullId) [AST.IfaceVarDec vecPar vectorTM] booleanTM
1437 -- return vec'length = 0
1438 nullExpr = AST.ReturnSm (Just $
1439 AST.PrimName (AST.NAttribute $
1440 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:=:
1442 rotlSpec = AST.Function (mkVHDLExtId rotlId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1443 -- variable res : fsvec_x (0 to vec'length-1);
1446 (AST.SubtypeIn vectorTM
1447 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1448 [AST.ToRange (AST.PrimLit "0")
1449 (AST.PrimName (AST.NAttribute $
1450 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1451 (AST.PrimLit "1")) ]))
1453 -- if null(vec) then res := vec else res := last(vec) & init(vec)
1454 rotlExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1455 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1456 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1458 (Just $ AST.Else [rotlExprRet])
1460 AST.NSimple resId AST.:=
1461 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId lastId))
1462 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1463 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1464 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1465 rotlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1466 rotrSpec = AST.Function (mkVHDLExtId rotrId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1467 -- variable res : fsvec_x (0 to vec'length-1);
1470 (AST.SubtypeIn vectorTM
1471 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1472 [AST.ToRange (AST.PrimLit "0")
1473 (AST.PrimName (AST.NAttribute $
1474 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1475 (AST.PrimLit "1")) ]))
1477 -- if null(vec) then res := vec else res := tail(vec) & head(vec)
1478 rotrExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1479 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1480 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1482 (Just $ AST.Else [rotrExprRet])
1484 AST.NSimple resId AST.:=
1485 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1486 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1487 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId headId))
1488 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1489 rotrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1490 reverseSpec = AST.Function (mkVHDLExtId reverseId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1493 (AST.SubtypeIn vectorTM
1494 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1495 [AST.ToRange (AST.PrimLit "0")
1496 (AST.PrimName (AST.NAttribute $
1497 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1498 (AST.PrimLit "1")) ]))
1500 -- for i in 0 to res'range loop
1501 -- res(vec'length-i-1) := vec(i);
1504 AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple rangeId) Nothing) [reverseAssign]
1505 -- res(vec'length-i-1) := vec(i);
1506 reverseAssign = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [destExp]) AST.:=
1507 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar)
1508 [AST.PrimName $ AST.NSimple iId]))
1509 where destExp = AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar)
1510 (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1511 AST.PrimName (AST.NSimple iId) AST.:-:
1514 reverseRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1517 -----------------------------------------------------------------------------
1518 -- A table of builtin functions
1519 -----------------------------------------------------------------------------
1521 -- A function that generates VHDL for a builtin function
1522 type BuiltinBuilder =
1523 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
1524 -> CoreSyn.CoreBndr -- ^ The function called
1525 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
1526 -- dictionary arguments).
1527 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
1528 -- ^ The corresponding VHDL concurrent statements and entities
1531 -- A map of a builtin function to VHDL function builder
1532 type NameTable = Map.Map String (Int, BuiltinBuilder )
1534 -- | The builtin functions we support. Maps a name to an argument count and a
1535 -- builder function.
1536 globalNameTable :: NameTable
1537 globalNameTable = Map.fromList
1538 [ (exId , (2, genFCall True ) )
1539 , (replaceId , (3, genFCall False ) )
1540 , (headId , (1, genFCall True ) )
1541 , (lastId , (1, genFCall True ) )
1542 , (tailId , (1, genFCall False ) )
1543 , (initId , (1, genFCall False ) )
1544 , (takeId , (2, genFCall False ) )
1545 , (dropId , (2, genFCall False ) )
1546 , (selId , (4, genFCall False ) )
1547 , (plusgtId , (2, genFCall False ) )
1548 , (ltplusId , (2, genFCall False ) )
1549 , (plusplusId , (2, genFCall False ) )
1550 , (mapId , (2, genMap ) )
1551 , (zipWithId , (3, genZipWith ) )
1552 , (foldlId , (3, genFoldl ) )
1553 , (foldrId , (3, genFoldr ) )
1554 , (zipId , (2, genZip ) )
1555 , (unzipId , (1, genUnzip ) )
1556 , (shiftlId , (2, genFCall False ) )
1557 , (shiftrId , (2, genFCall False ) )
1558 , (rotlId , (1, genFCall False ) )
1559 , (rotrId , (1, genFCall False ) )
1560 , (concatId , (1, genConcat ) )
1561 , (reverseId , (1, genFCall False ) )
1562 , (iteratenId , (3, genIteraten ) )
1563 , (iterateId , (2, genIterate ) )
1564 , (generatenId , (3, genGeneraten ) )
1565 , (generateId , (2, genGenerate ) )
1566 , (emptyId , (0, genFCall False ) )
1567 , (singletonId , (1, genFCall False ) )
1568 , (copynId , (2, genFCall False ) )
1569 , (copyId , (1, genCopy ) )
1570 , (lengthTId , (1, genFCall False ) )
1571 , (nullId , (1, genFCall False ) )
1572 , (hwxorId , (2, genOperator2 AST.Xor ) )
1573 , (hwandId , (2, genOperator2 AST.And ) )
1574 , (hworId , (2, genOperator2 AST.Or ) )
1575 , (hwnotId , (1, genOperator1 AST.Not ) )
1576 , (equalityId , (2, genOperator2 (AST.:=:) ) )
1577 , (inEqualityId , (2, genOperator2 (AST.:/=:) ) )
1578 , (ltId , (2, genOperator2 (AST.:<:) ) )
1579 , (lteqId , (2, genOperator2 (AST.:<=:) ) )
1580 , (gtId , (2, genOperator2 (AST.:>:) ) )
1581 , (gteqId , (2, genOperator2 (AST.:>=:) ) )
1582 , (boolOrId , (2, genOperator2 AST.Or ) )
1583 , (boolAndId , (2, genOperator2 AST.And ) )
1584 , (plusId , (2, genOperator2 (AST.:+:) ) )
1585 , (timesId , (2, genTimes ) )
1586 , (negateId , (1, genNegation ) )
1587 , (minusId , (2, genOperator2 (AST.:-:) ) )
1588 , (fromSizedWordId , (1, genFromSizedWord ) )
1589 , (fromIntegerId , (1, genFromInteger ) )
1590 , (resizeWordId , (1, genResize ) )
1591 , (resizeIntId , (1, genResize ) )
1592 , (sizedIntId , (1, genSizedInt ) )
1593 , (smallIntegerId , (1, genFromInteger ) )
1594 , (fstId , (1, genFst ) )
1595 , (sndId , (1, genSnd ) )
1596 , (blockRAMId , (5, genBlockRAM ) )
1597 , (splitId , (1, genSplit ) )
1598 --, (tfvecId , (1, genTFVec ) )
1599 , (minimumId , (2, error "\nFunction name: \"minimum\" is used internally, use another name"))