1 {-# LANGUAGE PackageImports #-}
3 module CLasH.VHDL.Generate where
6 import qualified Control.Monad as Monad
7 import qualified Data.Map as Map
9 import qualified Data.Either as Either
10 import qualified Control.Monad.Trans.State as State
11 import qualified "transformers" Control.Monad.Identity as Identity
13 import Data.Accessor.MonadState as MonadState
17 import qualified Language.VHDL.AST as AST
23 import qualified IdInfo
24 import qualified Literal
26 import qualified TyCon
29 import CLasH.VHDL.Constants
30 import CLasH.VHDL.VHDLTypes
31 import CLasH.VHDL.VHDLTools
32 import CLasH.Utils.Core.CoreTools
33 import CLasH.Utils.Pretty
35 -----------------------------------------------------------------------------
36 -- Functions to generate VHDL for builtin functions
37 -----------------------------------------------------------------------------
39 -- | A function to wrap a builder-like function that expects its arguments to
41 genExprArgs wrap dst func args = do
42 args' <- eitherCoreOrExprArgs args
45 eitherCoreOrExprArgs :: [Either CoreSyn.CoreExpr AST.Expr] -> VHDLSession [AST.Expr]
46 eitherCoreOrExprArgs args = mapM (Either.either ((MonadState.lift vsType) . varToVHDLExpr . exprToVar) return) args
48 -- | A function to wrap a builder-like function that expects its arguments to
51 (dst -> func -> [Var.Var] -> res)
52 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
53 genVarArgs wrap dst func args = wrap dst func args'
55 args' = map exprToVar exprargs
56 -- Check (rather crudely) that all arguments are CoreExprs
57 (exprargs, []) = Either.partitionEithers args
59 -- | A function to wrap a builder-like function that expects its arguments to
62 (dst -> func -> [Literal.Literal] -> res)
63 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
64 genLitArgs wrap dst func args = wrap dst func args'
66 args' = map exprToLit litargs
67 -- FIXME: Check if we were passed an CoreSyn.App
68 litargs = concat (map getLiterals exprargs)
69 (exprargs, []) = Either.partitionEithers args
71 -- | A function to wrap a builder-like function that produces an expression
72 -- and expects it to be assigned to the destination.
74 ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> VHDLSession AST.Expr)
75 -> ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> VHDLSession [AST.ConcSm])
76 genExprRes wrap dst func args = do
77 expr <- wrap dst func args
78 return $ [mkUncondAssign dst expr]
80 -- | Generate a binary operator application. The first argument should be a
81 -- constructor from the AST.Expr type, e.g. AST.And.
82 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
83 genOperator2 op = genExprArgs $ genExprRes (genOperator2' op)
84 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
85 genOperator2' op _ f [arg1, arg2] = return $ op arg1 arg2
87 -- | Generate a unary operator application
88 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
89 genOperator1 op = genExprArgs $ genExprRes (genOperator1' op)
90 genOperator1' :: (AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
91 genOperator1' op _ f [arg] = return $ op arg
93 -- | Generate a unary operator application
94 genNegation :: BuiltinBuilder
95 genNegation = genVarArgs $ genExprRes genNegation'
96 genNegation' :: dst -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession AST.Expr
97 genNegation' _ f [arg] = do
98 arg1 <- MonadState.lift vsType $ varToVHDLExpr arg
99 let ty = Var.varType arg
100 let (tycon, args) = Type.splitTyConApp ty
101 let name = Name.getOccString (TyCon.tyConName tycon)
103 "SizedInt" -> return $ AST.Neg arg1
104 otherwise -> error $ "\nGenerate.genNegation': Negation allowed for type: " ++ show name
106 -- | Generate a function call from the destination binder, function name and a
107 -- list of expressions (its arguments)
108 genFCall :: Bool -> BuiltinBuilder
109 genFCall switch = genExprArgs $ genExprRes (genFCall' switch)
110 genFCall' :: Bool -> Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
111 genFCall' switch (Left res) f args = do
112 let fname = varToString f
113 let el_ty = if switch then (Var.varType res) else ((tfvec_elem . Var.varType) res)
114 id <- MonadState.lift vsType $ vectorFunId el_ty fname
115 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
116 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
117 genFCall' _ (Right name) _ _ = error $ "\nGenerate.genFCall': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
119 genFromSizedWord :: BuiltinBuilder
120 genFromSizedWord = genExprArgs $ genExprRes genFromSizedWord'
121 genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
122 genFromSizedWord' (Left res) f args = do
123 let fname = varToString f
124 return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $
125 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
126 genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
128 genResize :: BuiltinBuilder
129 genResize = genExprArgs $ genExprRes genResize'
130 genResize' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> VHDLSession AST.Expr
131 genResize' (Left res) f [arg] = do {
132 ; let { ty = Var.varType res
133 ; (tycon, args) = Type.splitTyConApp ty
134 ; name = Name.getOccString (TyCon.tyConName tycon)
136 ; len <- case name of
137 "SizedInt" -> MonadState.lift vsType $ tfp_to_int (sized_int_len_ty ty)
138 "SizedWord" -> MonadState.lift vsType $ tfp_to_int (sized_word_len_ty ty)
139 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId resizeId))
140 [Nothing AST.:=>: AST.ADExpr arg, Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
142 genResize' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
144 -- FIXME: I'm calling genLitArgs which is very specific function,
145 -- which needs to be fixed as well
146 genFromInteger :: BuiltinBuilder
147 genFromInteger = genLitArgs $ genExprRes genFromInteger'
148 genFromInteger' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [Literal.Literal] -> VHDLSession AST.Expr
149 genFromInteger' (Left res) f lits = do {
150 ; let { ty = Var.varType res
151 ; (tycon, args) = Type.splitTyConApp ty
152 ; name = Name.getOccString (TyCon.tyConName tycon)
154 ; len <- case name of
155 "SizedInt" -> MonadState.lift vsType $ tfp_to_int (sized_int_len_ty ty)
156 "SizedWord" -> MonadState.lift vsType $ tfp_to_int (sized_word_len_ty ty)
157 ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId
158 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname))
159 [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
162 genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
164 genSizedInt :: BuiltinBuilder
165 genSizedInt = genFromInteger
167 genTFVec :: BuiltinBuilder
168 genTFVec (Left res) f [Left veclist] = do {
169 ; let (CoreSyn.Let (CoreSyn.Rec [(bndr, app@(CoreSyn.App _ _))]) rez) = veclist
170 ; let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
171 ; let valargs = get_val_args (Var.varType f) args
172 ; apps <- genApplication (Left bndr) f (map Left valargs)
173 ; (aap,kooi) <- reduceFSVECListToHsList rez
174 ; sigs <- mapM (\x -> MonadState.lift vsType $ varToVHDLExpr x) (bndr:aap)
175 ; let vecsigns = concatsigs sigs
176 ; let vecassign = mkUncondAssign (Left res) vecsigns
177 ; sig_dec_maybes <- mapM mkSigDec (bndr:aap)
178 ; let sig_decs = map (AST.BDISD) (Maybe.catMaybes $ sig_dec_maybes)
179 ; let block_label = mkVHDLExtId ("FSVec_" ++ (show (map varToString (bndr:aap))))
180 ; let block = AST.BlockSm block_label [] (AST.PMapAspect []) sig_decs (apps ++ kooi ++ [vecassign])
181 ; return $ [AST.CSBSm block]
184 concatsigs x = AST.Aggregate (map (\z -> AST.ElemAssoc Nothing z) x)
187 reduceFSVECListToHsList app@(CoreSyn.App _ letexpr) = do
189 (CoreSyn.Let (CoreSyn.Rec [(bndr, app@(CoreSyn.App _ _))]) rez) -> do
190 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
191 let valargs = get_val_args (Var.varType f) args
192 app <- genApplication (Left bndr) f (map Left valargs)
193 (vars, apps) <- reduceFSVECListToHsList rez
194 return ((bndr:vars),(app ++ apps))
195 otherwise -> return ([],[])
198 -- | Generate a generate statement for the builtin function "map"
199 genMap :: BuiltinBuilder
200 genMap (Left res) f [Left mapped_f, Left (Var arg)] = do {
201 -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL
202 -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since
203 -- we must index it (which we couldn't if it was a VHDL Expr, since only
204 -- VHDLNames can be indexed).
205 -- Setup the generate scheme
206 ; len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
207 -- TODO: Use something better than varToString
208 ; let { label = mkVHDLExtId ("mapVector" ++ (varToString res))
209 ; n_id = mkVHDLBasicId "n"
210 ; n_expr = idToVHDLExpr n_id
211 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
212 ; genScheme = AST.ForGn n_id range
213 -- Create the content of the generate statement: Applying the mapped_f to
214 -- each of the elements in arg, storing to each element in res
215 ; resname = mkIndexedName (varToVHDLName res) n_expr
216 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
217 ; (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f
218 ; valargs = get_val_args (Var.varType real_f) already_mapped_args
220 ; app_concsms <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr])
221 -- Return the generate statement
222 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
225 genMap' (Right name) _ _ = error $ "\nGenerate.genMap': Cannot generate map function call assigned to a VHDLName: " ++ show name
227 genZipWith :: BuiltinBuilder
228 genZipWith = genVarArgs genZipWith'
229 genZipWith' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
230 genZipWith' (Left res) f args@[zipped_f, arg1, arg2] = do {
231 -- Setup the generate scheme
232 ; len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
233 -- TODO: Use something better than varToString
234 ; let { label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
235 ; n_id = mkVHDLBasicId "n"
236 ; n_expr = idToVHDLExpr n_id
237 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
238 ; genScheme = AST.ForGn n_id range
239 -- Create the content of the generate statement: Applying the zipped_f to
240 -- each of the elements in arg1 and arg2, storing to each element in res
241 ; resname = mkIndexedName (varToVHDLName res) n_expr
242 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
243 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
245 ; app_concsms <- genApplication (Right resname) zipped_f [Right argexpr1, Right argexpr2]
246 -- Return the generate functions
247 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms]
250 genFoldl :: BuiltinBuilder
251 genFoldl = genFold True
253 genFoldr :: BuiltinBuilder
254 genFoldr = genFold False
256 genFold :: Bool -> BuiltinBuilder
257 genFold left = genVarArgs (genFold' left)
259 genFold' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
260 genFold' left res f args@[folded_f , start ,vec]= do
261 len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty (Var.varType vec))
262 genFold'' len left res f args
264 genFold'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
265 -- Special case for an empty input vector, just assign start to res
266 genFold'' len left (Left res) _ [_, start, vec] | len == 0 = do
267 arg <- MonadState.lift vsType $ varToVHDLExpr start
268 return [mkUncondAssign (Left res) arg]
270 genFold'' len left (Left res) f [folded_f, start, vec] = do
272 --len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
273 -- An expression for len-1
274 let len_min_expr = (AST.PrimLit $ show (len-1))
275 -- evec is (TFVec n), so it still needs an element type
276 let (nvec, _) = splitAppTy (Var.varType vec)
277 -- Put the type of the start value in nvec, this will be the type of our
279 let tmp_ty = Type.mkAppTy nvec (Var.varType start)
280 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
281 tmp_vhdl_ty <- MonadState.lift vsType $ vhdl_ty error_msg tmp_ty
282 -- Setup the generate scheme
283 let gen_label = mkVHDLExtId ("foldlVector" ++ (varToString vec))
284 let block_label = mkVHDLExtId ("foldlVector" ++ (varToString res))
285 let gen_range = if left then AST.ToRange (AST.PrimLit "0") len_min_expr
286 else AST.DownRange len_min_expr (AST.PrimLit "0")
287 let gen_scheme = AST.ForGn n_id gen_range
288 -- Make the intermediate vector
289 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
290 -- Create the generate statement
291 cells <- sequence [genFirstCell, genOtherCell]
292 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
293 -- Assign tmp[len-1] or tmp[0] to res
294 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr (if left then
295 (mkIndexedName tmp_name (AST.PrimLit $ show (len-1))) else
296 (mkIndexedName tmp_name (AST.PrimLit "0")))
297 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
298 return [AST.CSBSm block]
300 -- An id for the counter
301 n_id = mkVHDLBasicId "n"
302 n_cur = idToVHDLExpr n_id
303 -- An expression for previous n
304 n_prev = if left then (n_cur AST.:-: (AST.PrimLit "1"))
305 else (n_cur AST.:+: (AST.PrimLit "1"))
306 -- An id for the tmp result vector
307 tmp_id = mkVHDLBasicId "tmp"
308 tmp_name = AST.NSimple tmp_id
309 -- Generate parts of the fold
310 genFirstCell, genOtherCell :: VHDLSession AST.GenerateSm
312 len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
313 let cond_label = mkVHDLExtId "firstcell"
314 -- if n == 0 or n == len-1
315 let cond_scheme = AST.IfGn $ n_cur AST.:=: (if left then (AST.PrimLit "0")
316 else (AST.PrimLit $ show (len-1)))
317 -- Output to tmp[current n]
318 let resname = mkIndexedName tmp_name n_cur
320 argexpr1 <- MonadState.lift vsType $ varToVHDLExpr start
321 -- Input from vec[current n]
322 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
323 app_concsms <- genApplication (Right resname) folded_f ( if left then
324 [Right argexpr1, Right argexpr2]
326 [Right argexpr2, Right argexpr1]
328 -- Return the conditional generate part
329 return $ AST.GenerateSm cond_label cond_scheme [] app_concsms
332 len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
333 let cond_label = mkVHDLExtId "othercell"
334 -- if n > 0 or n < len-1
335 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (if left then (AST.PrimLit "0")
336 else (AST.PrimLit $ show (len-1)))
337 -- Output to tmp[current n]
338 let resname = mkIndexedName tmp_name n_cur
339 -- Input from tmp[previous n]
340 let argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
341 -- Input from vec[current n]
342 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
343 app_concsms <- genApplication (Right resname) folded_f ( if left then
344 [Right argexpr1, Right argexpr2]
346 [Right argexpr2, Right argexpr1]
348 -- Return the conditional generate part
349 return $ AST.GenerateSm cond_label cond_scheme [] app_concsms
351 -- | Generate a generate statement for the builtin function "zip"
352 genZip :: BuiltinBuilder
353 genZip = genVarArgs genZip'
354 genZip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
355 genZip' (Left res) f args@[arg1, arg2] = do {
356 -- Setup the generate scheme
357 ; len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
358 -- TODO: Use something better than varToString
359 ; let { label = mkVHDLExtId ("zipVector" ++ (varToString res))
360 ; n_id = mkVHDLBasicId "n"
361 ; n_expr = idToVHDLExpr n_id
362 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
363 ; genScheme = AST.ForGn n_id range
364 ; resname' = mkIndexedName (varToVHDLName res) n_expr
365 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
366 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
368 ; labels <- MonadState.lift vsType $ getFieldLabels (tfvec_elem (Var.varType res))
369 ; let { resnameA = mkSelectedName resname' (labels!!0)
370 ; resnameB = mkSelectedName resname' (labels!!1)
371 ; resA_assign = mkUncondAssign (Right resnameA) argexpr1
372 ; resB_assign = mkUncondAssign (Right resnameB) argexpr2
374 -- Return the generate functions
375 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
378 -- | Generate a generate statement for the builtin function "unzip"
379 genUnzip :: BuiltinBuilder
380 genUnzip = genVarArgs genUnzip'
381 genUnzip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
382 genUnzip' (Left res) f args@[arg] = do {
383 -- Setup the generate scheme
384 ; len <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
385 -- TODO: Use something better than varToString
386 ; let { label = mkVHDLExtId ("unzipVector" ++ (varToString res))
387 ; n_id = mkVHDLBasicId "n"
388 ; n_expr = idToVHDLExpr n_id
389 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
390 ; genScheme = AST.ForGn n_id range
391 ; resname' = varToVHDLName res
392 ; argexpr' = mkIndexedName (varToVHDLName arg) n_expr
394 ; reslabels <- MonadState.lift vsType $ getFieldLabels (Var.varType res)
395 ; arglabels <- MonadState.lift vsType $ getFieldLabels (tfvec_elem (Var.varType arg))
396 ; let { resnameA = mkIndexedName (mkSelectedName resname' (reslabels!!0)) n_expr
397 ; resnameB = mkIndexedName (mkSelectedName resname' (reslabels!!1)) n_expr
398 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!0)
399 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!1)
400 ; resA_assign = mkUncondAssign (Right resnameA) argexprA
401 ; resB_assign = mkUncondAssign (Right resnameB) argexprB
403 -- Return the generate functions
404 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
407 genCopy :: BuiltinBuilder
408 genCopy = genVarArgs genCopy'
409 genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
410 genCopy' (Left res) f args@[arg] =
412 resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others)
413 (AST.PrimName $ (varToVHDLName arg))]
414 out_assign = mkUncondAssign (Left res) resExpr
418 genConcat :: BuiltinBuilder
419 genConcat = genVarArgs genConcat'
420 genConcat' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
421 genConcat' (Left res) f args@[arg] = do {
422 -- Setup the generate scheme
423 ; len1 <- MonadState.lift vsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
424 ; let (_, nvec) = splitAppTy (Var.varType arg)
425 ; len2 <- MonadState.lift vsType $ tfp_to_int $ tfvec_len_ty nvec
426 -- TODO: Use something better than varToString
427 ; let { label = mkVHDLExtId ("concatVector" ++ (varToString res))
428 ; n_id = mkVHDLBasicId "n"
429 ; n_expr = idToVHDLExpr n_id
430 ; fromRange = n_expr AST.:*: (AST.PrimLit $ show len2)
431 ; genScheme = AST.ForGn n_id range
432 -- Create the content of the generate statement: Applying the mapped_f to
433 -- each of the elements in arg, storing to each element in res
434 ; toRange = (n_expr AST.:*: (AST.PrimLit $ show len2)) AST.:+: (AST.PrimLit $ show (len2-1))
435 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len1-1))
436 ; resname = vecSlice fromRange toRange
437 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
438 ; out_assign = mkUncondAssign (Right resname) argexpr
440 -- Return the generate statement
441 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [out_assign]]
444 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
445 (AST.ToRange init last))
447 genIteraten :: BuiltinBuilder
448 genIteraten dst f args = genIterate dst f (tail args)
450 genIterate :: BuiltinBuilder
451 genIterate = genIterateOrGenerate True
453 genGeneraten :: BuiltinBuilder
454 genGeneraten dst f args = genGenerate dst f (tail args)
456 genGenerate :: BuiltinBuilder
457 genGenerate = genIterateOrGenerate False
459 genIterateOrGenerate :: Bool -> BuiltinBuilder
460 genIterateOrGenerate iter = genVarArgs (genIterateOrGenerate' iter)
462 genIterateOrGenerate' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
463 genIterateOrGenerate' iter (Left res) f args = do
464 len <- MonadState.lift vsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
465 genIterateOrGenerate'' len iter (Left res) f args
467 genIterateOrGenerate'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> VHDLSession [AST.ConcSm]
468 -- Special case for an empty input vector, just assign start to res
469 genIterateOrGenerate'' len iter (Left res) _ [app_f, start] | len == 0 = return [mkUncondAssign (Left res) (AST.PrimLit "\"\"")]
471 genIterateOrGenerate'' len iter (Left res) f [app_f, start] = do
473 -- len <- MonadState.lift vsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
474 -- An expression for len-1
475 let len_min_expr = (AST.PrimLit $ show (len-1))
476 -- -- evec is (TFVec n), so it still needs an element type
477 -- let (nvec, _) = splitAppTy (Var.varType vec)
478 -- -- Put the type of the start value in nvec, this will be the type of our
479 -- -- temporary vector
480 let tmp_ty = Var.varType res
481 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
482 tmp_vhdl_ty <- MonadState.lift vsType $ vhdl_ty error_msg tmp_ty
483 -- Setup the generate scheme
484 let gen_label = mkVHDLExtId ("iterateVector" ++ (varToString start))
485 let block_label = mkVHDLExtId ("iterateVector" ++ (varToString res))
486 let gen_range = AST.ToRange (AST.PrimLit "0") len_min_expr
487 let gen_scheme = AST.ForGn n_id gen_range
488 -- Make the intermediate vector
489 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
490 -- Create the generate statement
491 cells <- sequence [genFirstCell, genOtherCell]
492 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
493 -- Assign tmp[len-1] or tmp[0] to res
494 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr tmp_name
495 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
496 return [AST.CSBSm block]
498 -- An id for the counter
499 n_id = mkVHDLBasicId "n"
500 n_cur = idToVHDLExpr n_id
501 -- An expression for previous n
502 n_prev = n_cur AST.:-: (AST.PrimLit "1")
503 -- An id for the tmp result vector
504 tmp_id = mkVHDLBasicId "tmp"
505 tmp_name = AST.NSimple tmp_id
506 -- Generate parts of the fold
507 genFirstCell, genOtherCell :: VHDLSession AST.GenerateSm
509 let cond_label = mkVHDLExtId "firstcell"
510 -- if n == 0 or n == len-1
511 let cond_scheme = AST.IfGn $ n_cur AST.:=: (AST.PrimLit "0")
512 -- Output to tmp[current n]
513 let resname = mkIndexedName tmp_name n_cur
515 argexpr <- MonadState.lift vsType $ varToVHDLExpr start
516 let startassign = mkUncondAssign (Right resname) argexpr
517 app_concsms <- genApplication (Right resname) app_f [Right argexpr]
518 -- Return the conditional generate part
519 return $ AST.GenerateSm cond_label cond_scheme [] (if iter then
526 let cond_label = mkVHDLExtId "othercell"
527 -- if n > 0 or n < len-1
528 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (AST.PrimLit "0")
529 -- Output to tmp[current n]
530 let resname = mkIndexedName tmp_name n_cur
531 -- Input from tmp[previous n]
532 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
533 app_concsms <- genApplication (Right resname) app_f [Right argexpr]
534 -- Return the conditional generate part
535 return $ AST.GenerateSm cond_label cond_scheme [] app_concsms
538 -----------------------------------------------------------------------------
539 -- Function to generate VHDL for applications
540 -----------------------------------------------------------------------------
542 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
543 -> CoreSyn.CoreBndr -- ^ The function to apply
544 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
545 -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements
546 genApplication dst f args = do
547 case Var.isGlobalId f of
549 signatures <- getA vsSignatures
550 -- This is a local id, so it should be a function whose definition we
551 -- have and which can be turned into a component instantiation.
552 case (Map.lookup f signatures) of
554 args' <- eitherCoreOrExprArgs args
555 -- We have a signature, this is a top level binding. Generate a
556 -- component instantiation.
557 let entity_id = ent_id signature
558 -- TODO: Using show here isn't really pretty, but we'll need some
559 -- unique-ish value...
560 let label = "comp_ins_" ++ (either show prettyShow) dst
561 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
562 return [mkComponentInst label entity_id portmaps]
564 -- No signature, so this must be a local variable reference. It
565 -- should have a representable type (and thus, no arguments) and a
566 -- signal should be generated for it. Just generate an
567 -- unconditional assignment here.
568 f' <- MonadState.lift vsType $ varToVHDLExpr f
569 return $ [mkUncondAssign dst f']
571 case Var.idDetails f of
572 IdInfo.DataConWorkId dc -> case dst of
573 -- It's a datacon. Create a record from its arguments.
575 -- We have the bndr, so we can get at the type
576 labels <- MonadState.lift vsType $ getFieldLabels (Var.varType bndr)
577 args' <- eitherCoreOrExprArgs args
578 return $ zipWith mkassign labels $ args'
580 mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
582 let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
583 mkUncondAssign (Right sel_name) arg
584 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconstructor application without an original binder"
585 IdInfo.DataConWrapId dc -> case dst of
586 -- It's a datacon. Create a record from its arguments.
588 case (Map.lookup (varToString f) globalNameTable) of
589 Just (arg_count, builder) ->
590 if length args == arg_count then
593 error $ "\nGenerate.genApplication(DataConWrapId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
594 Nothing -> error $ "\nGenerate.genApplication: Can't generate dataconwrapper: " ++ (show dc)
595 Right _ -> error $ "\nGenerate.genApplication: Can't generate dataconwrapper application without an original binder"
596 IdInfo.VanillaId -> do
597 -- It's a global value imported from elsewhere. These can be builtin
598 -- functions. Look up the function name in the name table and execute
599 -- the associated builder if there is any and the argument count matches
600 -- (this should always be the case if it typechecks, but just to be
602 case (Map.lookup (varToString f) globalNameTable) of
603 Just (arg_count, builder) ->
604 if length args == arg_count then
607 error $ "\nGenerate.genApplication(VanillaGlobal): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
608 Nothing -> return $ trace ("\nGenerate.genApplication(VanillaGlobal): Using function from another module that is not a known builtin: " ++ (pprString f)) []
609 IdInfo.ClassOpId cls -> do
610 -- FIXME: Not looking for what instance this class op is called for
611 -- Is quite stupid of course.
612 case (Map.lookup (varToString f) globalNameTable) of
613 Just (arg_count, builder) ->
614 if length args == arg_count then
617 error $ "\nGenerate.genApplication(ClassOpId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
618 Nothing -> error $ "\nGenerate.genApplication(ClassOpId): Using function from another module that is not a known builtin: " ++ pprString f
619 details -> error $ "\nGenerate.genApplication: Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
621 -----------------------------------------------------------------------------
622 -- Functions to generate functions dealing with vectors.
623 -----------------------------------------------------------------------------
625 -- Returns the VHDLId of the vector function with the given name for the given
626 -- element type. Generates -- this function if needed.
627 vectorFunId :: Type.Type -> String -> TypeSession AST.VHDLId
628 vectorFunId el_ty fname = do
629 let error_msg = "\nGenerate.vectorFunId: Can not construct vector function for element: " ++ pprString el_ty
630 elemTM <- vhdl_ty error_msg el_ty
631 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
632 -- the VHDLState or something.
633 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
634 typefuns <- getA vsTypeFuns
635 case Map.lookup (OrdType el_ty, fname) typefuns of
636 -- Function already generated, just return it
637 Just (id, _) -> return id
638 -- Function not generated yet, generate it
640 let functions = genUnconsVectorFuns elemTM vectorTM
641 case lookup fname functions of
643 modA vsTypeFuns $ Map.insert (OrdType el_ty, fname) (function_id, (fst body))
644 mapM_ (vectorFunId el_ty) (snd body)
646 Nothing -> error $ "\nGenerate.vectorFunId: I don't know how to generate vector function " ++ fname
648 function_id = mkVHDLExtId fname
650 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
651 -> AST.TypeMark -- ^ type of the vector
652 -> [(String, (AST.SubProgBody, [String]))]
653 genUnconsVectorFuns elemTM vectorTM =
654 [ (exId, (AST.SubProgBody exSpec [] [exExpr],[]))
655 , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr,replaceRet],[]))
656 , (lastId, (AST.SubProgBody lastSpec [] [lastExpr],[]))
657 , (initId, (AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet],[]))
658 , (takeId, (AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet],[]))
659 , (dropId, (AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet],[]))
660 , (plusgtId, (AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet],[]))
661 , (emptyId, (AST.SubProgBody emptySpec [AST.SPCD emptyVar] [emptyExpr],[]))
662 , (singletonId, (AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet],[]))
663 , (copynId, (AST.SubProgBody copynSpec [AST.SPVD copynVar] [copynExpr],[]))
664 , (selId, (AST.SubProgBody selSpec [AST.SPVD selVar] [selFor, selRet],[]))
665 , (ltplusId, (AST.SubProgBody ltplusSpec [AST.SPVD ltplusVar] [ltplusExpr, ltplusRet],[]))
666 , (plusplusId, (AST.SubProgBody plusplusSpec [AST.SPVD plusplusVar] [plusplusExpr, plusplusRet],[]))
667 , (lengthTId, (AST.SubProgBody lengthTSpec [] [lengthTExpr],[]))
668 , (shiftlId, (AST.SubProgBody shiftlSpec [AST.SPVD shiftlVar] [shiftlExpr, shiftlRet], [initId]))
669 , (shiftrId, (AST.SubProgBody shiftrSpec [AST.SPVD shiftrVar] [shiftrExpr, shiftrRet], [tailId]))
670 , (nullId, (AST.SubProgBody nullSpec [] [nullExpr], []))
671 , (rotlId, (AST.SubProgBody rotlSpec [AST.SPVD rotlVar] [rotlExpr, rotlRet], [nullId, lastId, initId]))
672 , (rotrId, (AST.SubProgBody rotrSpec [AST.SPVD rotrVar] [rotrExpr, rotrRet], [nullId, tailId, headId]))
673 , (reverseId, (AST.SubProgBody reverseSpec [AST.SPVD reverseVar] [reverseFor, reverseRet], []))
676 ixPar = AST.unsafeVHDLBasicId "ix"
677 vecPar = AST.unsafeVHDLBasicId "vec"
678 vec1Par = AST.unsafeVHDLBasicId "vec1"
679 vec2Par = AST.unsafeVHDLBasicId "vec2"
680 nPar = AST.unsafeVHDLBasicId "n"
681 iId = AST.unsafeVHDLBasicId "i"
683 aPar = AST.unsafeVHDLBasicId "a"
684 fPar = AST.unsafeVHDLBasicId "f"
685 sPar = AST.unsafeVHDLBasicId "s"
686 resId = AST.unsafeVHDLBasicId "res"
687 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
688 AST.IfaceVarDec ixPar naturalTM] elemTM
689 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
690 (AST.IndexedName (AST.NSimple vecPar) [AST.PrimName $
692 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
693 , AST.IfaceVarDec iPar naturalTM
694 , AST.IfaceVarDec aPar elemTM
696 -- variable res : fsvec_x (0 to vec'length-1);
699 (AST.SubtypeIn vectorTM
700 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
701 [AST.ToRange (AST.PrimLit "0")
702 (AST.PrimName (AST.NAttribute $
703 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
704 (AST.PrimLit "1")) ]))
706 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
707 replaceExpr = AST.NSimple resId AST.:=
708 (vecSlice (AST.PrimLit "0") (AST.PrimName (AST.NSimple iPar) AST.:-: AST.PrimLit "1") AST.:&:
709 AST.PrimName (AST.NSimple aPar) AST.:&:
710 vecSlice (AST.PrimName (AST.NSimple iPar) AST.:+: AST.PrimLit "1")
711 ((AST.PrimName (AST.NAttribute $
712 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))
713 AST.:-: AST.PrimLit "1"))
714 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
715 vecSlice init last = AST.PrimName (AST.NSlice
718 (AST.ToRange init last)))
719 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
720 -- return vec(vec'length-1);
721 lastExpr = AST.ReturnSm (Just $ (AST.PrimName $ AST.NIndexed (AST.IndexedName
723 [AST.PrimName (AST.NAttribute $
724 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
725 AST.:-: AST.PrimLit "1"])))
726 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
727 -- variable res : fsvec_x (0 to vec'length-2);
730 (AST.SubtypeIn vectorTM
731 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
732 [AST.ToRange (AST.PrimLit "0")
733 (AST.PrimName (AST.NAttribute $
734 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
735 (AST.PrimLit "2")) ]))
737 -- resAST.:= vec(0 to vec'length-2)
738 initExpr = AST.NSimple resId AST.:= (vecSlice
740 (AST.PrimName (AST.NAttribute $
741 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
742 AST.:-: AST.PrimLit "2"))
743 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
744 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
745 AST.IfaceVarDec vecPar vectorTM ] vectorTM
746 -- variable res : fsvec_x (0 to n-1);
749 (AST.SubtypeIn vectorTM
750 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
751 [AST.ToRange (AST.PrimLit "0")
752 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
753 (AST.PrimLit "1")) ]))
755 -- res AST.:= vec(0 to n-1)
756 takeExpr = AST.NSimple resId AST.:=
757 (vecSlice (AST.PrimLit "1")
758 (AST.PrimName (AST.NSimple $ nPar) AST.:-: AST.PrimLit "1"))
759 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
760 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
761 AST.IfaceVarDec vecPar vectorTM ] vectorTM
762 -- variable res : fsvec_x (0 to vec'length-n-1);
765 (AST.SubtypeIn vectorTM
766 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
767 [AST.ToRange (AST.PrimLit "0")
768 (AST.PrimName (AST.NAttribute $
769 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
770 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
772 -- res AST.:= vec(n to vec'length-1)
773 dropExpr = AST.NSimple resId AST.:= (vecSlice
774 (AST.PrimName $ AST.NSimple nPar)
775 (AST.PrimName (AST.NAttribute $
776 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
777 AST.:-: AST.PrimLit "1"))
778 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
779 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
780 AST.IfaceVarDec vecPar vectorTM] vectorTM
781 -- variable res : fsvec_x (0 to vec'length);
784 (AST.SubtypeIn vectorTM
785 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
786 [AST.ToRange (AST.PrimLit "0")
787 (AST.PrimName (AST.NAttribute $
788 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
790 plusgtExpr = AST.NSimple resId AST.:=
791 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
792 (AST.PrimName $ AST.NSimple vecPar))
793 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
794 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
797 (AST.SubtypeIn vectorTM Nothing)
798 (Just $ AST.PrimLit "\"\"")
799 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
800 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
802 -- variable res : fsvec_x (0 to 0) := (others => a);
805 (AST.SubtypeIn vectorTM
806 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
807 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
808 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
809 (AST.PrimName $ AST.NSimple aPar)])
810 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
811 copynSpec = AST.Function (mkVHDLExtId copynId) [AST.IfaceVarDec nPar naturalTM,
812 AST.IfaceVarDec aPar elemTM ] vectorTM
813 -- variable res : fsvec_x (0 to n-1) := (others => a);
816 (AST.SubtypeIn vectorTM
817 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
818 [AST.ToRange (AST.PrimLit "0")
819 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
820 (AST.PrimLit "1")) ]))
821 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
822 (AST.PrimName $ AST.NSimple aPar)])
824 copynExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
825 selSpec = AST.Function (mkVHDLExtId selId) [AST.IfaceVarDec fPar naturalTM,
826 AST.IfaceVarDec sPar naturalTM,
827 AST.IfaceVarDec nPar naturalTM,
828 AST.IfaceVarDec vecPar vectorTM ] vectorTM
829 -- variable res : fsvec_x (0 to n-1);
832 (AST.SubtypeIn vectorTM
833 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
834 [AST.ToRange (AST.PrimLit "0")
835 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
836 (AST.PrimLit "1")) ])
839 -- for i res'range loop
840 -- res(i) := vec(f+i*s);
842 selFor = AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple $ rangeId) Nothing) [selAssign]
843 -- res(i) := vec(f+i*s);
844 selAssign = let origExp = AST.PrimName (AST.NSimple fPar) AST.:+:
845 (AST.PrimName (AST.NSimple iId) AST.:*:
846 AST.PrimName (AST.NSimple sPar)) in
847 AST.NIndexed (AST.IndexedName (AST.NSimple resId) [AST.PrimName (AST.NSimple iId)]) AST.:=
848 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [origExp]))
850 selRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
851 ltplusSpec = AST.Function (mkVHDLExtId ltplusId) [AST.IfaceVarDec vecPar vectorTM,
852 AST.IfaceVarDec aPar elemTM] vectorTM
853 -- variable res : fsvec_x (0 to vec'length);
856 (AST.SubtypeIn vectorTM
857 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
858 [AST.ToRange (AST.PrimLit "0")
859 (AST.PrimName (AST.NAttribute $
860 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
862 ltplusExpr = AST.NSimple resId AST.:=
863 ((AST.PrimName $ AST.NSimple vecPar) AST.:&:
864 (AST.PrimName $ AST.NSimple aPar))
865 ltplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
866 plusplusSpec = AST.Function (mkVHDLExtId plusplusId) [AST.IfaceVarDec vec1Par vectorTM,
867 AST.IfaceVarDec vec2Par vectorTM]
869 -- variable res : fsvec_x (0 to vec1'length + vec2'length -1);
872 (AST.SubtypeIn vectorTM
873 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
874 [AST.ToRange (AST.PrimLit "0")
875 (AST.PrimName (AST.NAttribute $
876 AST.AttribName (AST.NSimple vec1Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:+:
877 AST.PrimName (AST.NAttribute $
878 AST.AttribName (AST.NSimple vec2Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
881 plusplusExpr = AST.NSimple resId AST.:=
882 ((AST.PrimName $ AST.NSimple vec1Par) AST.:&:
883 (AST.PrimName $ AST.NSimple vec2Par))
884 plusplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
885 lengthTSpec = AST.Function (mkVHDLExtId lengthTId) [AST.IfaceVarDec vecPar vectorTM] naturalTM
886 lengthTExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NAttribute $
887 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))
888 shiftlSpec = AST.Function (mkVHDLExtId shiftlId) [AST.IfaceVarDec vecPar vectorTM,
889 AST.IfaceVarDec aPar elemTM ] vectorTM
890 -- variable res : fsvec_x (0 to vec'length-1);
893 (AST.SubtypeIn vectorTM
894 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
895 [AST.ToRange (AST.PrimLit "0")
896 (AST.PrimName (AST.NAttribute $
897 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
898 (AST.PrimLit "1")) ]))
900 -- res := a & init(vec)
901 shiftlExpr = AST.NSimple resId AST.:=
902 (AST.PrimName (AST.NSimple aPar) AST.:&:
903 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
904 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
905 shiftlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
906 shiftrSpec = AST.Function (mkVHDLExtId shiftrId) [AST.IfaceVarDec vecPar vectorTM,
907 AST.IfaceVarDec aPar elemTM ] vectorTM
908 -- variable res : fsvec_x (0 to vec'length-1);
911 (AST.SubtypeIn vectorTM
912 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
913 [AST.ToRange (AST.PrimLit "0")
914 (AST.PrimName (AST.NAttribute $
915 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
916 (AST.PrimLit "1")) ]))
918 -- res := tail(vec) & a
919 shiftrExpr = AST.NSimple resId AST.:=
920 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
921 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
922 (AST.PrimName (AST.NSimple aPar)))
924 shiftrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
925 nullSpec = AST.Function (mkVHDLExtId nullId) [AST.IfaceVarDec vecPar vectorTM] booleanTM
926 -- return vec'length = 0
927 nullExpr = AST.ReturnSm (Just $
928 AST.PrimName (AST.NAttribute $
929 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:=:
931 rotlSpec = AST.Function (mkVHDLExtId rotlId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
932 -- variable res : fsvec_x (0 to vec'length-1);
935 (AST.SubtypeIn vectorTM
936 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
937 [AST.ToRange (AST.PrimLit "0")
938 (AST.PrimName (AST.NAttribute $
939 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
940 (AST.PrimLit "1")) ]))
942 -- if null(vec) then res := vec else res := last(vec) & init(vec)
943 rotlExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
944 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
945 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
947 (Just $ AST.Else [rotlExprRet])
949 AST.NSimple resId AST.:=
950 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId lastId))
951 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
952 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
953 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
954 rotlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
955 rotrSpec = AST.Function (mkVHDLExtId rotrId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
956 -- variable res : fsvec_x (0 to vec'length-1);
959 (AST.SubtypeIn vectorTM
960 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
961 [AST.ToRange (AST.PrimLit "0")
962 (AST.PrimName (AST.NAttribute $
963 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
964 (AST.PrimLit "1")) ]))
966 -- if null(vec) then res := vec else res := tail(vec) & head(vec)
967 rotrExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
968 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
969 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
971 (Just $ AST.Else [rotrExprRet])
973 AST.NSimple resId AST.:=
974 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
975 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
976 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId headId))
977 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
978 rotrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
979 reverseSpec = AST.Function (mkVHDLExtId reverseId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
982 (AST.SubtypeIn vectorTM
983 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
984 [AST.ToRange (AST.PrimLit "0")
985 (AST.PrimName (AST.NAttribute $
986 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
987 (AST.PrimLit "1")) ]))
989 -- for i in 0 to res'range loop
990 -- res(vec'length-i-1) := vec(i);
993 AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple $ rangeId) Nothing) [reverseAssign]
994 -- res(vec'length-i-1) := vec(i);
995 reverseAssign = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [destExp]) AST.:=
996 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar)
997 [AST.PrimName $ AST.NSimple iId]))
998 where destExp = AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar)
999 (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1000 AST.PrimName (AST.NSimple iId) AST.:-:
1003 reverseRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1006 -----------------------------------------------------------------------------
1007 -- A table of builtin functions
1008 -----------------------------------------------------------------------------
1010 -- | The builtin functions we support. Maps a name to an argument count and a
1011 -- builder function.
1012 globalNameTable :: NameTable
1013 globalNameTable = Map.fromList
1014 [ (exId , (2, genFCall False ) )
1015 , (replaceId , (3, genFCall False ) )
1016 , (headId , (1, genFCall True ) )
1017 , (lastId , (1, genFCall True ) )
1018 , (tailId , (1, genFCall False ) )
1019 , (initId , (1, genFCall False ) )
1020 , (takeId , (2, genFCall False ) )
1021 , (dropId , (2, genFCall False ) )
1022 , (selId , (4, genFCall False ) )
1023 , (plusgtId , (2, genFCall False ) )
1024 , (ltplusId , (2, genFCall False ) )
1025 , (plusplusId , (2, genFCall False ) )
1026 , (mapId , (2, genMap ) )
1027 , (zipWithId , (3, genZipWith ) )
1028 , (foldlId , (3, genFoldl ) )
1029 , (foldrId , (3, genFoldr ) )
1030 , (zipId , (2, genZip ) )
1031 , (unzipId , (1, genUnzip ) )
1032 , (shiftlId , (2, genFCall False ) )
1033 , (shiftrId , (2, genFCall False ) )
1034 , (rotlId , (1, genFCall False ) )
1035 , (rotrId , (1, genFCall False ) )
1036 , (concatId , (1, genConcat ) )
1037 , (reverseId , (1, genFCall False ) )
1038 , (iteratenId , (3, genIteraten ) )
1039 , (iterateId , (2, genIterate ) )
1040 , (generatenId , (3, genGeneraten ) )
1041 , (generateId , (2, genGenerate ) )
1042 , (emptyId , (0, genFCall False ) )
1043 , (singletonId , (1, genFCall False ) )
1044 , (copynId , (2, genFCall False ) )
1045 , (copyId , (1, genCopy ) )
1046 , (lengthTId , (1, genFCall False ) )
1047 , (nullId , (1, genFCall False ) )
1048 , (hwxorId , (2, genOperator2 AST.Xor ) )
1049 , (hwandId , (2, genOperator2 AST.And ) )
1050 , (hworId , (2, genOperator2 AST.Or ) )
1051 , (hwnotId , (1, genOperator1 AST.Not ) )
1052 , (plusId , (2, genOperator2 (AST.:+:) ) )
1053 , (timesId , (2, genOperator2 (AST.:*:) ) )
1054 , (negateId , (1, genNegation ) )
1055 , (minusId , (2, genOperator2 (AST.:-:) ) )
1056 , (fromSizedWordId , (1, genFromSizedWord ) )
1057 , (fromIntegerId , (1, genFromInteger ) )
1058 , (resizeId , (1, genResize ) )
1059 , (sizedIntId , (1, genSizedInt ) )
1060 , (tfvecId , (1, genTFVec ) )