1 module CLasH.VHDL.Generate where
4 import qualified Data.List as List
5 import qualified Data.Map as Map
6 import qualified Control.Monad as Monad
8 import qualified Data.Either as Either
9 import qualified Data.Accessor.Monad.Trans.State as MonadState
12 import qualified Language.VHDL.AST as AST
15 import qualified CoreSyn
19 import qualified IdInfo
20 import qualified Literal
22 import qualified TyCon
25 import CLasH.Translator.TranslatorTypes
26 import CLasH.VHDL.Constants
27 import CLasH.VHDL.VHDLTypes
28 import CLasH.VHDL.VHDLTools
30 import CLasH.Utils.Core.CoreTools
31 import CLasH.Utils.Pretty
32 import qualified CLasH.Normalize as Normalize
34 -----------------------------------------------------------------------------
35 -- Functions to generate VHDL for user-defined functions.
36 -----------------------------------------------------------------------------
38 -- | Create an entity for a given function
41 -> TranslatorSession Entity -- ^ The resulting entity
43 getEntity fname = makeCached fname tsEntities $ do
44 expr <- Normalize.getNormalized fname
45 -- Split the normalized expression
46 let (args, binds, res) = Normalize.splitNormalized expr
47 -- Generate ports for all non-empty types
48 args' <- catMaybesM $ mapM mkMap args
49 -- TODO: Handle Nothing
51 count <- MonadState.get tsEntityCounter
52 let vhdl_id = mkVHDLBasicId $ varToString fname ++ "Component_" ++ show count
53 MonadState.set tsEntityCounter (count + 1)
54 let ent_decl = createEntityAST vhdl_id args' res'
55 let signature = Entity vhdl_id args' res' ent_decl
59 --[(SignalId, SignalInfo)]
61 -> TranslatorSession (Maybe Port)
64 --info = Maybe.fromMaybe
65 -- (error $ "Signal not found in the name map? This should not happen!")
67 -- Assume the bndr has a valid VHDL id already
70 error_msg = "\nVHDL.createEntity.mkMap: Can not create entity: " ++ pprString fname ++ "\nbecause no type can be created for port: " ++ pprString bndr
72 type_mark_maybe <- MonadState.lift tsType $ vhdlTy error_msg ty
73 case type_mark_maybe of
74 Just type_mark -> return $ Just (id, type_mark)
75 Nothing -> return Nothing
78 -- | Create the VHDL AST for an entity
80 AST.VHDLId -- ^ The name of the function
81 -> [Port] -- ^ The entity's arguments
82 -> Maybe Port -- ^ The entity's result
83 -> AST.EntityDec -- ^ The entity with the ent_decl filled in as well
85 createEntityAST vhdl_id args res =
86 AST.EntityDec vhdl_id ports
88 -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
89 ports = map (mkIfaceSigDec AST.In) args
90 ++ (Maybe.maybeToList res_port)
91 ++ [clk_port,resetn_port]
92 -- Add a clk port if we have state
93 clk_port = AST.IfaceSigDec clockId AST.In std_logicTM
94 resetn_port = AST.IfaceSigDec resetId AST.In std_logicTM
95 res_port = fmap (mkIfaceSigDec AST.Out) res
97 -- | Create a port declaration
99 AST.Mode -- ^ The mode for the port (In / Out)
100 -> Port -- ^ The id and type for the port
101 -> AST.IfaceSigDec -- ^ The resulting port declaration
103 mkIfaceSigDec mode (id, ty) = AST.IfaceSigDec id mode ty
105 -- | Create an architecture for a given function
107 CoreSyn.CoreBndr -- ^ The function to get an architecture for
108 -> TranslatorSession (Architecture, [CoreSyn.CoreBndr])
109 -- ^ The architecture for this function
111 getArchitecture fname = makeCached fname tsArchitectures $ do
112 expr <- Normalize.getNormalized fname
113 -- Split the normalized expression
114 let (args, binds, res) = Normalize.splitNormalized expr
116 -- Get the entity for this function
117 signature <- getEntity fname
118 let entity_id = ent_id signature
120 -- Create signal declarations for all binders in the let expression, except
121 -- for the output port (that will already have an output port declared in
123 sig_dec_maybes <- mapM (mkSigDec . fst) (filter ((/=res).fst) binds)
124 let sig_decs = Maybe.catMaybes sig_dec_maybes
125 -- Process each bind, resulting in info about state variables and concurrent
127 (state_vars, sms) <- Monad.mapAndUnzipM dobind binds
128 let (in_state_maybes, out_state_maybes) = unzip state_vars
129 let (statementss, used_entitiess) = unzip sms
130 -- Get initial state, if it's there
131 initSmap <- MonadState.get tsInitStates
132 let init_state = Map.lookup fname initSmap
133 -- Create a state proc, if needed
134 (state_proc, resbndr) <- case (Maybe.catMaybes in_state_maybes, Maybe.catMaybes out_state_maybes, init_state) of
135 ([in_state], [out_state], Nothing) -> do
136 nonEmpty <- hasNonEmptyType in_state
138 then error ("No initial state defined for: " ++ show fname)
140 ([in_state], [out_state], Just resetval) -> do
141 nonEmpty <- hasNonEmptyType in_state
143 then mkStateProcSm (in_state, out_state, resetval)
144 else error ("Initial state defined for function with only substate: " ++ show fname)
145 ([], [], Just _) -> error $ "Initial state defined for state-less function: " ++ show fname
146 ([], [], Nothing) -> return ([],[])
147 (ins, outs, res) -> error $ "Weird use of state in " ++ show fname ++ ". In: " ++ show ins ++ " Out: " ++ show outs
148 -- Join the create statements and the (optional) state_proc
149 let statements = concat statementss ++ state_proc
150 -- Create the architecture
151 let arch = AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) statements
152 let used_entities = (concat used_entitiess) ++ resbndr
153 return (arch, used_entities)
155 dobind :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The bind to process
156 -> TranslatorSession ((Maybe CoreSyn.CoreBndr, Maybe CoreSyn.CoreBndr), ([AST.ConcSm], [CoreSyn.CoreBndr]))
157 -- ^ ((Input state variable, output state variable), (statements, used entities))
158 -- newtype unpacking is just a cast
159 dobind (bndr, unpacked@(CoreSyn.Cast packed coercion))
160 | hasStateType packed && not (hasStateType unpacked)
161 = return ((Just bndr, Nothing), ([], []))
162 -- With simplCore, newtype packing is just a cast
163 dobind (bndr, packed@(CoreSyn.Cast unpacked@(CoreSyn.Var state) coercion))
164 | hasStateType packed && not (hasStateType unpacked)
165 = return ((Nothing, Just state), ([], []))
166 -- Without simplCore, newtype packing uses a data constructor
167 dobind (bndr, (CoreSyn.App (CoreSyn.App (CoreSyn.Var con) (CoreSyn.Type _)) (CoreSyn.Var state)))
169 = return ((Nothing, Just state), ([], []))
170 -- Anything else is handled by mkConcSm
173 return ((Nothing, Nothing), sms)
176 (CoreSyn.CoreBndr, CoreSyn.CoreBndr, CoreSyn.CoreBndr) -- ^ The current state, new state and reset variables
177 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr]) -- ^ The resulting statements
178 mkStateProcSm (old, new, res) = do
179 let error_msg = "\nVHDL.mkSigDec: Can not make signal declaration for type: \n" ++ pprString res
180 type_mark_old_maybe <- MonadState.lift tsType $ vhdlTy error_msg (Var.varType old)
181 let type_mark_old = Maybe.fromMaybe
182 (error $ "\nGenerate.mkStateProcSm: empty type for state? Type: " ++ pprString (Var.varType old))
184 type_mark_res_maybe <- MonadState.lift tsType $ vhdlTy error_msg (Var.varType res)
185 let type_mark_res' = Maybe.fromMaybe
186 (error $ "\nGenerate.mkStateProcSm: empty type for initial state? Type: " ++ pprString (Var.varType res))
188 let type_mark_res = if type_mark_old == type_mark_res' then
191 error $ "Initial state has different type than state type, state type: " ++ show type_mark_old ++ ", init type: " ++ show type_mark_res'
192 let resvalid = mkVHDLExtId $ varToString res ++ "val"
193 let resvaldec = AST.BDISD $ AST.SigDec resvalid type_mark_res Nothing
194 let reswform = AST.Wform [AST.WformElem (AST.PrimName $ AST.NSimple resvalid) Nothing]
195 let res_assign = AST.SigAssign (varToVHDLName old) reswform
196 let blocklabel = mkVHDLBasicId "state"
197 let statelabel = mkVHDLBasicId "stateupdate"
198 let rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
199 let wform = AST.Wform [AST.WformElem (AST.PrimName $ varToVHDLName new) Nothing]
200 let clk_assign = AST.SigAssign (varToVHDLName old) wform
201 let rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clockId)]
202 let resetn_is_low = (AST.PrimName $ AST.NSimple resetId) AST.:=: (AST.PrimLit "'0'")
203 signature <- getEntity res
204 let entity_id = ent_id signature
205 let reslabel = "resetval_" ++ ((prettyShow . varToVHDLName) res)
206 let portmaps = mkAssocElems [] (AST.NSimple resvalid) signature
207 let reset_statement = mkComponentInst reslabel entity_id portmaps
208 let clk_statement = [AST.ElseIf rising_edge_clk [clk_assign]]
209 let statement = AST.IfSm resetn_is_low [res_assign] clk_statement Nothing
210 let stateupdate = AST.CSPSm $ AST.ProcSm statelabel [clockId,resetId,resvalid] [statement]
211 let block = AST.CSBSm $ AST.BlockSm blocklabel [] (AST.PMapAspect []) [resvaldec] [reset_statement,stateupdate]
212 return ([block],[res])
214 -- | Transforms a core binding into a VHDL concurrent statement
216 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
217 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
218 -- ^ The corresponding VHDL concurrent statements and entities
222 -- Ignore Cast expressions, they should not longer have any meaning as long as
223 -- the type works out. Throw away state repacking
224 mkConcSm (bndr, to@(CoreSyn.Cast from ty))
225 | hasStateType to && hasStateType from
227 mkConcSm (bndr, CoreSyn.Cast expr ty) = mkConcSm (bndr, expr)
229 -- Simple a = b assignments are just like applications, but without arguments.
230 -- We can't just generate an unconditional assignment here, since b might be a
231 -- top level binding (e.g., a function with no arguments).
232 mkConcSm (bndr, CoreSyn.Var v) =
233 genApplication (Left bndr) v []
235 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
236 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
237 let valargs = get_val_args (Var.varType f) args
238 genApplication (Left bndr) f (map Left valargs)
240 -- A single alt case must be a selector. This means the scrutinee is a simple
241 -- variable, the alternative is a dataalt with a single non-wild binder that
243 mkConcSm (bndr, expr@(CoreSyn.Case (CoreSyn.Var scrut) b ty [alt]))
244 -- Don't generate VHDL for substate extraction
245 | hasStateType bndr = return ([], [])
248 (CoreSyn.DataAlt dc, bndrs, (CoreSyn.Var sel_bndr)) -> do
249 nonemptysel <- hasNonEmptyType sel_bndr
252 bndrs' <- Monad.filterM hasNonEmptyType bndrs
253 case List.elemIndex sel_bndr bndrs' of
255 htypeScrt <- MonadState.lift tsType $ mkHTypeEither (Var.varType scrut)
256 htypeBndr <- MonadState.lift tsType $ mkHTypeEither (Var.varType bndr)
257 case htypeScrt == htypeBndr of
259 let sel_name = varToVHDLName scrut
260 let sel_expr = AST.PrimName sel_name
261 return ([mkUncondAssign (Left bndr) sel_expr], [])
264 Right (AggrType _ _) -> do
265 labels <- MonadState.lift tsType $ getFieldLabels (Id.idType scrut)
266 let label = labels!!i
267 let sel_name = mkSelectedName (varToVHDLName scrut) label
268 let sel_expr = AST.PrimName sel_name
269 return ([mkUncondAssign (Left bndr) sel_expr], [])
270 _ -> do -- error $ "DIE!"
271 let sel_name = varToVHDLName scrut
272 let sel_expr = AST.PrimName sel_name
273 return ([mkUncondAssign (Left bndr) sel_expr], [])
274 Nothing -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case: result is not one of the binders\n" ++ (pprString expr)
276 -- A selector case that selects a state value, ignore it.
279 _ -> error $ "\nVHDL.mkConcSM: Not in normal form: Not a selector case:\n" ++ (pprString expr)
281 -- Multiple case alt are be conditional assignments and have only wild
282 -- binders in the alts and only variables in the case values and a variable
283 -- for a scrutinee. We check the constructor of the second alt, since the
284 -- first is the default case, if there is any.
286 -- mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) b ty [(_, _, CoreSyn.Var false), (con, _, CoreSyn.Var true)])) = do
287 -- scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut
288 -- altcon <- MonadState.lift tsType $ altconToVHDLExpr con
289 -- let cond_expr = scrut' AST.:=: altcon
290 -- true_expr <- MonadState.lift tsType $ varToVHDLExpr true
291 -- false_expr <- MonadState.lift tsType $ varToVHDLExpr false
292 -- return ([mkCondAssign (Left bndr) cond_expr true_expr false_expr], [])
293 mkConcSm (bndr, (CoreSyn.Case (CoreSyn.Var scrut) _ _ (alt:alts))) = do --error "\nVHDL.mkConcSm: Not in normal form: Case statement with more than two alternatives"
294 scrut' <- MonadState.lift tsType $ varToVHDLExpr scrut
295 -- Omit first condition, which is the default
296 altcons <- MonadState.lift tsType $ mapM (altconToVHDLExpr . (\(con,_,_) -> con)) alts
297 let cond_exprs = map (\x -> scrut' AST.:=: x) altcons
298 -- Rotate expressions to the left, so that the expression related to the default case is the last
299 exprs <- MonadState.lift tsType $ mapM (varToVHDLExpr . (\(_,_,CoreSyn.Var expr) -> expr)) (alts ++ [alt])
300 return ([mkAltsAssign (Left bndr) cond_exprs exprs], [])
302 mkConcSm (_, CoreSyn.Case _ _ _ _) = error "\nVHDL.mkConcSm: Not in normal form: Case statement has does not have a simple variable as scrutinee"
303 mkConcSm (bndr, expr) = error $ "\nVHDL.mkConcSM: Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
305 -----------------------------------------------------------------------------
306 -- Functions to generate VHDL for builtin functions
307 -----------------------------------------------------------------------------
309 -- | A function to wrap a builder-like function that expects its arguments to
311 genExprArgs wrap dst func args = do
312 args' <- argsToVHDLExprs args
315 -- | Turn the all lefts into VHDL Expressions.
316 argsToVHDLExprs :: [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.Expr]
317 argsToVHDLExprs = catMaybesM . (mapM argToVHDLExpr)
319 argToVHDLExpr :: Either CoreSyn.CoreExpr AST.Expr -> TranslatorSession (Maybe AST.Expr)
320 argToVHDLExpr (Left expr) = MonadState.lift tsType $ do
321 let errmsg = "Generate.argToVHDLExpr: Using non-representable type? Should not happen!"
322 ty_maybe <- vhdlTy errmsg expr
325 vhdl_expr <- varToVHDLExpr $ exprToVar expr
326 return $ Just vhdl_expr
327 Nothing -> return Nothing
329 argToVHDLExpr (Right expr) = return $ Just expr
331 -- A function to wrap a builder-like function that generates no component
334 (dst -> func -> args -> TranslatorSession [AST.ConcSm])
335 -> (dst -> func -> args -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr]))
336 genNoInsts wrap dst func args = do
337 concsms <- wrap dst func args
340 -- | A function to wrap a builder-like function that expects its arguments to
343 (dst -> func -> [Var.Var] -> res)
344 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> res)
345 genVarArgs wrap dst func args = wrap dst func args'
347 args' = map exprToVar args''
348 -- Check (rather crudely) that all arguments are CoreExprs
349 args'' = case Either.partitionEithers args of
350 (exprargs, []) -> exprargs
351 (exprsargs, rest) -> error $ "\nGenerate.genVarArgs: expect varargs but found ast exprs:" ++ (show rest)
353 -- | A function to wrap a builder-like function that expects its arguments to
356 (dst -> func -> [Literal.Literal] -> TranslatorSession [AST.ConcSm])
357 -> (dst -> func -> [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.ConcSm])
358 genLitArgs wrap dst func args = do
359 hscenv <- MonadState.lift tsType $ MonadState.get tsHscEnv
360 let (exprargs, []) = Either.partitionEithers args
361 -- FIXME: Check if we were passed an CoreSyn.App
362 let litargs = concatMap (getLiterals hscenv) exprargs
363 let args' = map exprToLit litargs
366 -- | A function to wrap a builder-like function that produces an expression
367 -- and expects it to be assigned to the destination.
369 ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession AST.Expr)
370 -> ((Either CoreSyn.CoreBndr AST.VHDLName) -> func -> [arg] -> TranslatorSession [AST.ConcSm])
371 genExprRes wrap dst func args = do
372 expr <- wrap dst func args
373 return [mkUncondAssign dst expr]
375 -- | Generate a binary operator application. The first argument should be a
376 -- constructor from the AST.Expr type, e.g. AST.And.
377 genOperator2 :: (AST.Expr -> AST.Expr -> AST.Expr) -> BuiltinBuilder
378 genOperator2 op = genNoInsts $ genExprArgs $ genExprRes (genOperator2' op)
379 genOperator2' :: (AST.Expr -> AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
380 genOperator2' op _ f [arg1, arg2] = return $ op arg1 arg2
382 -- | Generate a unary operator application
383 genOperator1 :: (AST.Expr -> AST.Expr) -> BuiltinBuilder
384 genOperator1 op = genNoInsts $ genExprArgs $ genExprRes (genOperator1' op)
385 genOperator1' :: (AST.Expr -> AST.Expr) -> dst -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
386 genOperator1' op _ f [arg] = return $ op arg
388 -- | Generate a unary operator application
389 genNegation :: BuiltinBuilder
390 genNegation = genNoInsts $ genVarArgs $ genExprRes genNegation'
391 genNegation' :: dst -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession AST.Expr
392 genNegation' _ f [arg] = do
393 arg1 <- MonadState.lift tsType $ varToVHDLExpr arg
394 let ty = Var.varType arg
395 let (tycon, args) = Type.splitTyConApp ty
396 let name = Name.getOccString (TyCon.tyConName tycon)
398 "SizedInt" -> return $ AST.Neg arg1
399 otherwise -> error $ "\nGenerate.genNegation': Negation not allowed for type: " ++ show name
401 -- | Generate a function call from the destination binder, function name and a
402 -- list of expressions (its arguments)
403 genFCall :: Bool -> BuiltinBuilder
404 genFCall switch = genNoInsts $ genExprArgs $ genExprRes (genFCall' switch)
405 genFCall' :: Bool -> Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
406 genFCall' switch (Left res) f args = do
407 let fname = varToString f
408 let el_ty = if switch then (Var.varType res) else ((tfvec_elem . Var.varType) res)
409 id <- MonadState.lift tsType $ vectorFunId el_ty fname
410 return $ AST.PrimFCall $ AST.FCall (AST.NSimple id) $
411 map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
412 genFCall' _ (Right name) _ _ = error $ "\nGenerate.genFCall': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
414 genFromSizedWord :: BuiltinBuilder
415 genFromSizedWord = genNoInsts $ genExprArgs genFromSizedWord'
416 genFromSizedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm]
417 genFromSizedWord' (Left res) f args@[arg] =
418 return [mkUncondAssign (Left res) arg]
419 -- let fname = varToString f
420 -- return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId toIntegerId)) $
421 -- map (\exp -> Nothing AST.:=>: AST.ADExpr exp) args
422 genFromSizedWord' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
424 genFromRangedWord :: BuiltinBuilder
425 genFromRangedWord = genNoInsts $ genExprArgs $ genExprRes genFromRangedWord'
426 genFromRangedWord' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
427 genFromRangedWord' (Left res) f [arg] = do {
428 ; let { ty = Var.varType res
429 ; (tycon, args) = Type.splitTyConApp ty
430 ; name = Name.getOccString (TyCon.tyConName tycon)
432 ; len <- MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
433 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId resizeId))
434 [Nothing AST.:=>: AST.ADExpr arg, Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
436 genFromRangedWord' (Right name) _ _ = error $ "\nGenerate.genFromRangedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
438 genResize :: BuiltinBuilder
439 genResize = genNoInsts $ genExprArgs $ genExprRes genResize'
440 genResize' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
441 genResize' (Left res) f [arg] = do {
442 ; let { ty = Var.varType res
443 ; (tycon, args) = Type.splitTyConApp ty
444 ; name = Name.getOccString (TyCon.tyConName tycon)
446 ; len <- case name of
447 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
448 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
449 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId resizeId))
450 [Nothing AST.:=>: AST.ADExpr arg, Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
452 genResize' (Right name) _ _ = error $ "\nGenerate.genFromSizedWord': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
454 genTimes :: BuiltinBuilder
455 genTimes = genNoInsts $ genExprArgs $ genExprRes genTimes'
456 genTimes' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession AST.Expr
457 genTimes' (Left res) f [arg1,arg2] = do {
458 ; let { ty = Var.varType res
459 ; (tycon, args) = Type.splitTyConApp ty
460 ; name = Name.getOccString (TyCon.tyConName tycon)
462 ; len <- case name of
463 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
464 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
465 "RangedWord" -> do { ubound <- MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty)
466 ; let bitsize = floor (logBase 2 (fromInteger (toInteger ubound)))
469 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId resizeId))
470 [Nothing AST.:=>: AST.ADExpr (arg1 AST.:*: arg2), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
472 genTimes' (Right name) _ _ = error $ "\nGenerate.genTimes': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
474 -- FIXME: I'm calling genLitArgs which is very specific function,
475 -- which needs to be fixed as well
476 genFromInteger :: BuiltinBuilder
477 genFromInteger = genNoInsts $ genLitArgs $ genExprRes genFromInteger'
478 genFromInteger' :: Either CoreSyn.CoreBndr AST.VHDLName -> CoreSyn.CoreBndr -> [Literal.Literal] -> TranslatorSession AST.Expr
479 genFromInteger' (Left res) f lits = do {
480 ; let { ty = Var.varType res
481 ; (tycon, args) = Type.splitTyConApp ty
482 ; name = Name.getOccString (TyCon.tyConName tycon)
484 ; len <- case name of
485 "SizedInt" -> MonadState.lift tsType $ tfp_to_int (sized_int_len_ty ty)
486 "SizedWord" -> MonadState.lift tsType $ tfp_to_int (sized_word_len_ty ty)
488 ; bound <- MonadState.lift tsType $ tfp_to_int (ranged_word_bound_ty ty)
489 ; return $ floor (logBase 2 (fromInteger (toInteger (bound)))) + 1
491 ; let fname = case name of "SizedInt" -> toSignedId ; "SizedWord" -> toUnsignedId ; "RangedWord" -> toUnsignedId
492 ; return $ AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLBasicId fname))
493 [Nothing AST.:=>: AST.ADExpr (AST.PrimLit (show (last lits))), Nothing AST.:=>: AST.ADExpr( AST.PrimLit (show len))]
497 genFromInteger' (Right name) _ _ = error $ "\nGenerate.genFromInteger': Cannot generate builtin function call assigned to a VHDLName: " ++ show name
499 genSizedInt :: BuiltinBuilder
500 genSizedInt = genFromInteger
503 -- | Generate a Builder for the builtin datacon TFVec
504 genTFVec :: BuiltinBuilder
505 genTFVec (Left res) f [Left (CoreSyn.Let (CoreSyn.Rec letBinders) letRes)] = do {
506 -- Generate Assignments for all the binders
507 ; letAssigns <- mapM genBinderAssign letBinders
508 -- Generate assignments for the result (which might be another let binding)
509 ; (resBinders,resAssignments) <- genResAssign letRes
510 -- Get all the Assigned binders
511 ; let assignedBinders = Maybe.catMaybes (map fst letAssigns)
512 -- Make signal names for all the assigned binders
513 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) (assignedBinders ++ resBinders)
514 -- Assign all the signals to the resulting vector
515 ; let { vecsigns = mkAggregateSignal sigs
516 ; vecassign = mkUncondAssign (Left res) vecsigns
518 -- Generate all the signal declaration for the assigned binders
519 ; sig_dec_maybes <- mapM mkSigDec (assignedBinders ++ resBinders)
520 ; let { sig_decs = map (AST.BDISD) (Maybe.catMaybes $ sig_dec_maybes)
521 -- Setup the VHDL Block
522 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
523 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) sig_decs ((concat (map snd letAssigns)) ++ resAssignments ++ [vecassign])
525 -- Return the block statement coressponding to the TFVec literal
526 ; return $ [AST.CSBSm block]
529 genBinderAssign :: (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -> TranslatorSession (Maybe CoreSyn.CoreBndr, [AST.ConcSm])
530 -- For now we only translate applications
531 genBinderAssign (bndr, app@(CoreSyn.App _ _)) = do
532 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
533 let valargs = get_val_args (Var.varType f) args
534 apps <- genApplication (Left bndr) f (map Left valargs)
535 return (Just bndr, apps)
536 genBinderAssign _ = return (Nothing,[])
537 genResAssign :: CoreSyn.CoreExpr -> TranslatorSession ([CoreSyn.CoreBndr], [AST.ConcSm])
538 genResAssign app@(CoreSyn.App _ letexpr) = do
540 (CoreSyn.Let (CoreSyn.Rec letbndrs) letres) -> do
541 letapps <- mapM genBinderAssign letbndrs
542 let bndrs = Maybe.catMaybes (map fst letapps)
543 let app = (map snd letapps)
544 (vars, apps) <- genResAssign letres
545 return ((bndrs ++ vars),((concat app) ++ apps))
546 otherwise -> return ([],[])
547 genResAssign _ = return ([],[])
549 genTFVec (Left res) f [Left app@(CoreSyn.App _ _)] = do {
550 ; let { elems = reduceCoreListToHsList app
551 -- Make signal names for all the binders
552 ; binders = map (\expr -> case expr of
554 otherwise -> error $ "\nGenerate.genTFVec: Cannot generate TFVec: "
555 ++ show res ++ ", with elems:\n" ++ show elems ++ "\n" ++ pprString elems) elems
557 ; sigs <- mapM (\x -> MonadState.lift tsType $ varToVHDLExpr x) binders
558 -- Assign all the signals to the resulting vector
559 ; let { vecsigns = mkAggregateSignal sigs
560 ; vecassign = mkUncondAssign (Left res) vecsigns
561 -- Setup the VHDL Block
562 ; block_label = mkVHDLExtId ("TFVec_" ++ show (varToString res))
563 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) [] [vecassign]
565 -- Return the block statement coressponding to the TFVec literal
566 ; return $ [AST.CSBSm block]
569 genTFVec (Left name) _ [Left xs] = error $ "\nGenerate.genTFVec: Cannot generate TFVec: " ++ show name ++ ", with elems:\n" ++ show xs ++ "\n" ++ pprString xs
571 genTFVec (Right name) _ _ = error $ "\nGenerate.genTFVec: Cannot generate TFVec assigned to VHDLName: " ++ show name
573 -- | Generate a generate statement for the builtin function "map"
574 genMap :: BuiltinBuilder
575 genMap (Left res) f [Left mapped_f, Left (CoreSyn.Var arg)] = do {
576 -- mapped_f must be a CoreExpr (since we can't represent functions as VHDL
577 -- expressions). arg must be a CoreExpr (and should be a CoreSyn.Var), since
578 -- we must index it (which we couldn't if it was a VHDL Expr, since only
579 -- VHDLNames can be indexed).
580 -- Setup the generate scheme
581 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
582 -- TODO: Use something better than varToString
583 ; let { label = mkVHDLExtId ("mapVector" ++ (varToString res))
584 ; n_id = mkVHDLBasicId "n"
585 ; n_expr = idToVHDLExpr n_id
586 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
587 ; genScheme = AST.ForGn n_id range
588 -- Create the content of the generate statement: Applying the mapped_f to
589 -- each of the elements in arg, storing to each element in res
590 ; resname = mkIndexedName (varToVHDLName res) n_expr
591 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
592 ; (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs mapped_f
593 ; valargs = get_val_args (Var.varType real_f) already_mapped_args
595 ; (app_concsms, used) <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr])
596 -- Return the generate statement
597 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
600 genMap' (Right name) _ _ = error $ "\nGenerate.genMap': Cannot generate map function call assigned to a VHDLName: " ++ show name
602 genZipWith :: BuiltinBuilder
603 genZipWith (Left res) f args@[Left zipped_f, Left (CoreSyn.Var arg1), Left (CoreSyn.Var arg2)] = do {
604 -- Setup the generate scheme
605 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
606 -- TODO: Use something better than varToString
607 ; let { label = mkVHDLExtId ("zipWithVector" ++ (varToString res))
608 ; n_id = mkVHDLBasicId "n"
609 ; n_expr = idToVHDLExpr n_id
610 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
611 ; genScheme = AST.ForGn n_id range
612 -- Create the content of the generate statement: Applying the zipped_f to
613 -- each of the elements in arg1 and arg2, storing to each element in res
614 ; resname = mkIndexedName (varToVHDLName res) n_expr
615 ; (CoreSyn.Var real_f, already_mapped_args) = CoreSyn.collectArgs zipped_f
616 ; valargs = get_val_args (Var.varType real_f) already_mapped_args
617 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
618 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
620 ; (app_concsms, used) <- genApplication (Right resname) real_f (map Left valargs ++ [Right argexpr1, Right argexpr2])
621 -- Return the generate functions
622 ; return ([AST.CSGSm $ AST.GenerateSm label genScheme [] app_concsms], used)
625 genFoldl :: BuiltinBuilder
626 genFoldl = genFold True
628 genFoldr :: BuiltinBuilder
629 genFoldr = genFold False
631 genFold :: Bool -> BuiltinBuilder
632 genFold left = genVarArgs (genFold' left)
634 genFold' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
635 genFold' left res f args@[folded_f , start ,vec]= do
636 len <- MonadState.lift tsType $ tfp_to_int (tfvec_len_ty (Var.varType vec))
637 genFold'' len left res f args
639 genFold'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
640 -- Special case for an empty input vector, just assign start to res
641 genFold'' len left (Left res) _ [_, start, vec] | len == 0 = do
642 arg <- MonadState.lift tsType $ varToVHDLExpr start
643 return ([mkUncondAssign (Left res) arg], [])
645 genFold'' len left (Left res) f [folded_f, start, vec] = do
647 --len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
648 -- An expression for len-1
649 let len_min_expr = (AST.PrimLit $ show (len-1))
650 -- evec is (TFVec n), so it still needs an element type
651 let (nvec, _) = Type.splitAppTy (Var.varType vec)
652 -- Put the type of the start value in nvec, this will be the type of our
654 let tmp_ty = Type.mkAppTy nvec (Var.varType start)
655 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
656 -- TODO: Handle Nothing
657 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdlTy error_msg tmp_ty
658 -- Setup the generate scheme
659 let gen_label = mkVHDLExtId ("foldlVector" ++ (varToString vec))
660 let block_label = mkVHDLExtId ("foldlVector" ++ (varToString res))
661 let gen_range = if left then AST.ToRange (AST.PrimLit "0") len_min_expr
662 else AST.DownRange len_min_expr (AST.PrimLit "0")
663 let gen_scheme = AST.ForGn n_id gen_range
664 -- Make the intermediate vector
665 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
666 -- Create the generate statement
667 cells' <- sequence [genFirstCell, genOtherCell]
668 let (cells, useds) = unzip cells'
669 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
670 -- Assign tmp[len-1] or tmp[0] to res
671 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr (if left then
672 (mkIndexedName tmp_name (AST.PrimLit $ show (len-1))) else
673 (mkIndexedName tmp_name (AST.PrimLit "0")))
674 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
675 return ([AST.CSBSm block], concat useds)
677 -- An id for the counter
678 n_id = mkVHDLBasicId "n"
679 n_cur = idToVHDLExpr n_id
680 -- An expression for previous n
681 n_prev = if left then (n_cur AST.:-: (AST.PrimLit "1"))
682 else (n_cur AST.:+: (AST.PrimLit "1"))
683 -- An id for the tmp result vector
684 tmp_id = mkVHDLBasicId "tmp"
685 tmp_name = AST.NSimple tmp_id
686 -- Generate parts of the fold
687 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
689 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
690 let cond_label = mkVHDLExtId "firstcell"
691 -- if n == 0 or n == len-1
692 let cond_scheme = AST.IfGn $ n_cur AST.:=: (if left then (AST.PrimLit "0")
693 else (AST.PrimLit $ show (len-1)))
694 -- Output to tmp[current n]
695 let resname = mkIndexedName tmp_name n_cur
697 argexpr1 <- MonadState.lift tsType $ varToVHDLExpr start
698 -- Input from vec[current n]
699 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
700 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
701 [Right argexpr1, Right argexpr2]
703 [Right argexpr2, Right argexpr1]
705 -- Return the conditional generate part
706 return (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
709 len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vec
710 let cond_label = mkVHDLExtId "othercell"
711 -- if n > 0 or n < len-1
712 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (if left then (AST.PrimLit "0")
713 else (AST.PrimLit $ show (len-1)))
714 -- Output to tmp[current n]
715 let resname = mkIndexedName tmp_name n_cur
716 -- Input from tmp[previous n]
717 let argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
718 -- Input from vec[current n]
719 let argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName vec) n_cur
720 (app_concsms, used) <- genApplication (Right resname) folded_f ( if left then
721 [Right argexpr1, Right argexpr2]
723 [Right argexpr2, Right argexpr1]
725 -- Return the conditional generate part
726 return (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
728 -- | Generate a generate statement for the builtin function "zip"
729 genZip :: BuiltinBuilder
730 genZip = genNoInsts $ genVarArgs genZip'
731 genZip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
732 genZip' (Left res) f args@[arg1, arg2] = do {
733 -- Setup the generate scheme
734 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) res
735 -- TODO: Use something better than varToString
736 ; let { label = mkVHDLExtId ("zipVector" ++ (varToString res))
737 ; n_id = mkVHDLBasicId "n"
738 ; n_expr = idToVHDLExpr n_id
739 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
740 ; genScheme = AST.ForGn n_id range
741 ; resname' = mkIndexedName (varToVHDLName res) n_expr
742 ; argexpr1 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg1) n_expr
743 ; argexpr2 = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg2) n_expr
745 ; labels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType res))
746 ; let { resnameA = mkSelectedName resname' (labels!!0)
747 ; resnameB = mkSelectedName resname' (labels!!1)
748 ; resA_assign = mkUncondAssign (Right resnameA) argexpr1
749 ; resB_assign = mkUncondAssign (Right resnameB) argexpr2
751 -- Return the generate functions
752 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
755 -- | Generate a generate statement for the builtin function "fst"
756 genFst :: BuiltinBuilder
757 genFst = genNoInsts $ genVarArgs genFst'
758 genFst' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
759 genFst' (Left res) f args@[arg] = do {
760 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg)
761 ; let { argexpr' = varToVHDLName arg
762 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!0)
763 ; assign = mkUncondAssign (Left res) argexprA
765 -- Return the generate functions
769 -- | Generate a generate statement for the builtin function "snd"
770 genSnd :: BuiltinBuilder
771 genSnd = genNoInsts $ genVarArgs genSnd'
772 genSnd' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
773 genSnd' (Left res) f args@[arg] = do {
774 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType arg)
775 ; let { argexpr' = varToVHDLName arg
776 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (labels!!1)
777 ; assign = mkUncondAssign (Left res) argexprB
779 -- Return the generate functions
783 -- | Generate a generate statement for the builtin function "unzip"
784 genUnzip :: BuiltinBuilder
785 genUnzip = genNoInsts $ genVarArgs genUnzip'
786 genUnzip' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
787 genUnzip' (Left res) f args@[arg] = do
788 let error_msg = "\nGenerate.genUnzip: Cannot generate unzip call: " ++ pprString res ++ " = " ++ pprString f ++ " " ++ pprString arg
789 htype <- MonadState.lift tsType $ mkHType error_msg (Var.varType arg)
790 -- Prepare a unconditional assignment, for the case when either part
791 -- of the unzip is a state variable, which will disappear in the
792 -- resulting VHDL, making the the unzip no longer required.
794 -- A normal vector containing two-tuples
795 VecType _ (AggrType _ [_, _]) -> do {
796 -- Setup the generate scheme
797 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
798 -- TODO: Use something better than varToString
799 ; let { label = mkVHDLExtId ("unzipVector" ++ (varToString res))
800 ; n_id = mkVHDLBasicId "n"
801 ; n_expr = idToVHDLExpr n_id
802 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len-1))
803 ; genScheme = AST.ForGn n_id range
804 ; resname' = varToVHDLName res
805 ; argexpr' = mkIndexedName (varToVHDLName arg) n_expr
807 ; reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
808 ; arglabels <- MonadState.lift tsType $ getFieldLabels (tfvec_elem (Var.varType arg))
809 ; let { resnameA = mkIndexedName (mkSelectedName resname' (reslabels!!0)) n_expr
810 ; resnameB = mkIndexedName (mkSelectedName resname' (reslabels!!1)) n_expr
811 ; argexprA = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!0)
812 ; argexprB = vhdlNameToVHDLExpr $ mkSelectedName argexpr' (arglabels!!1)
813 ; resA_assign = mkUncondAssign (Right resnameA) argexprA
814 ; resB_assign = mkUncondAssign (Right resnameB) argexprB
816 -- Return the generate functions
817 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [resA_assign,resB_assign]]
819 -- Both elements of the tuple were state, so they've disappeared. No
820 -- need to do anything
821 VecType _ (AggrType _ []) -> return []
822 -- A vector containing aggregates with more than two elements?
823 VecType _ (AggrType _ _) -> error $ "Unzipping a value that is not a vector of two-tuples? Value: " ++ pprString arg ++ "\nType: " ++ pprString (Var.varType arg)
824 -- One of the elements of the tuple was state, so there won't be a
825 -- tuple (record) in the VHDL output. We can just do a plain
828 argexpr <- MonadState.lift tsType $ varToVHDLExpr arg
829 return [mkUncondAssign (Left res) argexpr]
830 _ -> error $ "Unzipping a value that is not a vector? Value: " ++ pprString arg ++ "\nType: " ++ pprString (Var.varType arg) ++ "\nhtype: " ++ show htype
832 genCopy :: BuiltinBuilder
833 genCopy = genNoInsts genCopy'
834 genCopy' :: (Either CoreSyn.CoreBndr AST.VHDLName ) -> CoreSyn.CoreBndr -> [Either CoreSyn.CoreExpr AST.Expr] -> TranslatorSession [AST.ConcSm]
835 genCopy' (Left res) f [arg] = do {
836 ; [arg'] <- argsToVHDLExprs [arg]
837 ; let { resExpr = AST.Aggregate [AST.ElemAssoc (Just AST.Others) arg']
838 ; out_assign = mkUncondAssign (Left res) resExpr
840 ; return [out_assign]
843 genConcat :: BuiltinBuilder
844 genConcat = genNoInsts $ genVarArgs genConcat'
845 genConcat' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
846 genConcat' (Left res) f args@[arg] = do {
847 -- Setup the generate scheme
848 ; len1 <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) arg
849 ; let (_, nvec) = Type.splitAppTy (Var.varType arg)
850 ; len2 <- MonadState.lift tsType $ tfp_to_int $ tfvec_len_ty nvec
851 -- TODO: Use something better than varToString
852 ; let { label = mkVHDLExtId ("concatVector" ++ (varToString res))
853 ; n_id = mkVHDLBasicId "n"
854 ; n_expr = idToVHDLExpr n_id
855 ; fromRange = n_expr AST.:*: (AST.PrimLit $ show len2)
856 ; genScheme = AST.ForGn n_id range
857 -- Create the content of the generate statement: Applying the mapped_f to
858 -- each of the elements in arg, storing to each element in res
859 ; toRange = (n_expr AST.:*: (AST.PrimLit $ show len2)) AST.:+: (AST.PrimLit $ show (len2-1))
860 ; range = AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len1-1))
861 ; resname = vecSlice fromRange toRange
862 ; argexpr = vhdlNameToVHDLExpr $ mkIndexedName (varToVHDLName arg) n_expr
863 ; out_assign = mkUncondAssign (Right resname) argexpr
865 -- Return the generate statement
866 ; return [AST.CSGSm $ AST.GenerateSm label genScheme [] [out_assign]]
869 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
870 (AST.ToRange init last))
872 genIteraten :: BuiltinBuilder
873 genIteraten dst f args = genIterate dst f (tail args)
875 genIterate :: BuiltinBuilder
876 genIterate = genIterateOrGenerate True
878 genGeneraten :: BuiltinBuilder
879 genGeneraten dst f args = genGenerate dst f (tail args)
881 genGenerate :: BuiltinBuilder
882 genGenerate = genIterateOrGenerate False
884 genIterateOrGenerate :: Bool -> BuiltinBuilder
885 genIterateOrGenerate iter = genVarArgs (genIterateOrGenerate' iter)
887 genIterateOrGenerate' :: Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
888 genIterateOrGenerate' iter (Left res) f args = do
889 len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
890 genIterateOrGenerate'' len iter (Left res) f args
892 genIterateOrGenerate'' :: Int -> Bool -> (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
893 -- Special case for an empty input vector, just assign start to res
894 genIterateOrGenerate'' len iter (Left res) _ [app_f, start] | len == 0 = return ([mkUncondAssign (Left res) (AST.PrimLit "\"\"")], [])
896 genIterateOrGenerate'' len iter (Left res) f [app_f, start] = do
898 -- len <- MonadState.lift tsType $ tfp_to_int ((tfvec_len_ty . Var.varType) res)
899 -- An expression for len-1
900 let len_min_expr = (AST.PrimLit $ show (len-1))
901 -- -- evec is (TFVec n), so it still needs an element type
902 -- let (nvec, _) = splitAppTy (Var.varType vec)
903 -- -- Put the type of the start value in nvec, this will be the type of our
904 -- -- temporary vector
905 let tmp_ty = Var.varType res
906 let error_msg = "\nGenerate.genFold': Can not construct temp vector for element type: " ++ pprString tmp_ty
907 -- TODO: Handle Nothing
908 Just tmp_vhdl_ty <- MonadState.lift tsType $ vhdlTy error_msg tmp_ty
909 -- Setup the generate scheme
910 let gen_label = mkVHDLExtId ("iterateVector" ++ (varToString start))
911 let block_label = mkVHDLExtId ("iterateVector" ++ (varToString res))
912 let gen_range = AST.ToRange (AST.PrimLit "0") len_min_expr
913 let gen_scheme = AST.ForGn n_id gen_range
914 -- Make the intermediate vector
915 let tmp_dec = AST.BDISD $ AST.SigDec tmp_id tmp_vhdl_ty Nothing
916 -- Create the generate statement
917 cells' <- sequence [genFirstCell, genOtherCell]
918 let (cells, useds) = unzip cells'
919 let gen_sm = AST.GenerateSm gen_label gen_scheme [] (map AST.CSGSm cells)
920 -- Assign tmp[len-1] or tmp[0] to res
921 let out_assign = mkUncondAssign (Left res) $ vhdlNameToVHDLExpr tmp_name
922 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [tmp_dec] [AST.CSGSm gen_sm, out_assign]
923 return ([AST.CSBSm block], concat useds)
925 -- An id for the counter
926 n_id = mkVHDLBasicId "n"
927 n_cur = idToVHDLExpr n_id
928 -- An expression for previous n
929 n_prev = n_cur AST.:-: (AST.PrimLit "1")
930 -- An id for the tmp result vector
931 tmp_id = mkVHDLBasicId "tmp"
932 tmp_name = AST.NSimple tmp_id
933 -- Generate parts of the fold
934 genFirstCell, genOtherCell :: TranslatorSession (AST.GenerateSm, [CoreSyn.CoreBndr])
936 let cond_label = mkVHDLExtId "firstcell"
937 -- if n == 0 or n == len-1
938 let cond_scheme = AST.IfGn $ n_cur AST.:=: (AST.PrimLit "0")
939 -- Output to tmp[current n]
940 let resname = mkIndexedName tmp_name n_cur
942 argexpr <- MonadState.lift tsType $ varToVHDLExpr start
943 let startassign = mkUncondAssign (Right resname) argexpr
944 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
945 -- Return the conditional generate part
946 let gensm = AST.GenerateSm cond_label cond_scheme [] (if iter then
954 let cond_label = mkVHDLExtId "othercell"
955 -- if n > 0 or n < len-1
956 let cond_scheme = AST.IfGn $ n_cur AST.:/=: (AST.PrimLit "0")
957 -- Output to tmp[current n]
958 let resname = mkIndexedName tmp_name n_cur
959 -- Input from tmp[previous n]
960 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName tmp_name n_prev
961 (app_concsms, used) <- genApplication (Right resname) app_f [Right argexpr]
962 -- Return the conditional generate part
963 return (AST.GenerateSm cond_label cond_scheme [] app_concsms, used)
965 genBlockRAM :: BuiltinBuilder
966 genBlockRAM = genNoInsts $ genExprArgs genBlockRAM'
968 genBlockRAM' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [AST.Expr] -> TranslatorSession [AST.ConcSm]
969 genBlockRAM' (Left res) f args@[data_in,rdaddr,wraddr,wrenable] = do
971 let (tup,data_out) = Type.splitAppTy (Var.varType res)
972 let (tup',ramvec) = Type.splitAppTy tup
973 let Just realram = Type.coreView ramvec
974 let Just (tycon, types) = Type.splitTyConApp_maybe realram
975 Just ram_vhdl_ty <- MonadState.lift tsType $ vhdlTy "wtf" (head types)
976 -- Make the intermediate vector
977 let ram_dec = AST.BDISD $ AST.SigDec ram_id ram_vhdl_ty Nothing
978 -- Get the data_out name
979 -- reslabels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
980 let resname = varToVHDLName res
981 -- let resname = mkSelectedName resname' (reslabels!!0)
982 let rdaddr_int = genExprFCall (mkVHDLBasicId toIntegerId) rdaddr
983 let argexpr = vhdlNameToVHDLExpr $ mkIndexedName (AST.NSimple ram_id) rdaddr_int
984 let assign = mkUncondAssign (Right resname) argexpr
985 let block_label = mkVHDLExtId ("blockRAM" ++ (varToString res))
986 let block = AST.BlockSm block_label [] (AST.PMapAspect []) [ram_dec] [assign, mkUpdateProcSm]
987 return [AST.CSBSm block]
989 ram_id = mkVHDLBasicId "ram"
990 mkUpdateProcSm :: AST.ConcSm
991 mkUpdateProcSm = AST.CSPSm $ AST.ProcSm proclabel [clockId] [statement]
993 proclabel = mkVHDLBasicId "updateRAM"
994 rising_edge = mkVHDLBasicId "rising_edge"
995 wraddr_int = genExprFCall (mkVHDLBasicId toIntegerId) wraddr
996 ramloc = mkIndexedName (AST.NSimple ram_id) wraddr_int
997 wform = AST.Wform [AST.WformElem data_in Nothing]
998 ramassign = AST.SigAssign ramloc wform
999 rising_edge_clk = genExprFCall rising_edge (AST.PrimName $ AST.NSimple clockId)
1000 statement = AST.IfSm (AST.And rising_edge_clk wrenable) [ramassign] [] Nothing
1002 genSplit :: BuiltinBuilder
1003 genSplit = genNoInsts $ genVarArgs genSplit'
1005 genSplit' :: (Either CoreSyn.CoreBndr AST.VHDLName) -> CoreSyn.CoreBndr -> [Var.Var] -> TranslatorSession [AST.ConcSm]
1006 genSplit' (Left res) f args@[vecIn] = do {
1007 ; labels <- MonadState.lift tsType $ getFieldLabels (Var.varType res)
1008 ; len <- MonadState.lift tsType $ tfp_to_int $ (tfvec_len_ty . Var.varType) vecIn
1009 ; let { block_label = mkVHDLExtId ("split" ++ (varToString vecIn))
1010 ; halflen = round ((fromIntegral len) / 2)
1011 ; rangeL = vecSlice (AST.PrimLit "0") (AST.PrimLit $ show (halflen - 1))
1012 ; rangeR = vecSlice (AST.PrimLit $ show halflen) (AST.PrimLit $ show (len - 1))
1013 ; resname = varToVHDLName res
1014 ; resnameL = mkSelectedName resname (labels!!0)
1015 ; resnameR = mkSelectedName resname (labels!!1)
1016 ; argexprL = vhdlNameToVHDLExpr rangeL
1017 ; argexprR = vhdlNameToVHDLExpr rangeR
1018 ; out_assignL = mkUncondAssign (Right resnameL) argexprL
1019 ; out_assignR = mkUncondAssign (Right resnameR) argexprR
1020 ; block = AST.BlockSm block_label [] (AST.PMapAspect []) [] [out_assignL, out_assignR]
1022 ; return [AST.CSBSm block]
1025 vecSlice init last = AST.NSlice (AST.SliceName (varToVHDLName res)
1026 (AST.ToRange init last))
1027 -----------------------------------------------------------------------------
1028 -- Function to generate VHDL for applications
1029 -----------------------------------------------------------------------------
1031 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ Where to store the result?
1032 -> CoreSyn.CoreBndr -- ^ The function to apply
1033 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The arguments to apply
1034 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
1035 -- ^ The corresponding VHDL concurrent statements and entities
1037 genApplication dst f args = do
1038 nonemptydst <- case dst of
1039 Left bndr -> hasNonEmptyType bndr
1040 Right _ -> return True
1043 if Var.isGlobalId f then
1044 case Var.idDetails f of
1045 IdInfo.DataConWorkId dc -> case dst of
1046 -- It's a datacon. Create a record from its arguments.
1048 -- We have the bndr, so we can get at the type
1049 htype <- MonadState.lift tsType $ mkHTypeEither (Var.varType bndr)
1050 let argsNostate = filter (\x -> not (either hasStateType (\x -> False) x)) args
1053 [arg'] <- argsToVHDLExprs [arg]
1054 return ([mkUncondAssign dst arg'], [])
1057 Right (AggrType _ _) -> do
1058 labels <- MonadState.lift tsType $ getFieldLabels (Var.varType bndr)
1059 args' <- argsToVHDLExprs argsNostate
1060 return (zipWith mkassign labels args', [])
1062 mkassign :: AST.VHDLId -> AST.Expr -> AST.ConcSm
1063 mkassign label arg =
1064 let sel_name = mkSelectedName ((either varToVHDLName id) dst) label in
1065 mkUncondAssign (Right sel_name) arg
1066 _ -> do -- error $ "DIE!"
1067 args' <- argsToVHDLExprs argsNostate
1068 return ([mkUncondAssign dst (head args')], [])
1069 Right _ -> error "\nGenerate.genApplication(DataConWorkId): Can't generate dataconstructor application without an original binder"
1070 IdInfo.DataConWrapId dc -> case dst of
1071 -- It's a datacon. Create a record from its arguments.
1073 case (Map.lookup (varToString f) globalNameTable) of
1074 Just (arg_count, builder) ->
1075 if length args == arg_count then
1078 error $ "\nGenerate.genApplication(DataConWrapId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
1079 Nothing -> error $ "\nGenerate.genApplication(DataConWrapId): Can't generate dataconwrapper: " ++ (show dc)
1080 Right _ -> error "\nGenerate.genApplication(DataConWrapId): Can't generate dataconwrapper application without an original binder"
1082 -- It's a global value imported from elsewhere. These can be builtin
1083 -- functions. Look up the function name in the name table and execute
1084 -- the associated builder if there is any and the argument count matches
1085 -- (this should always be the case if it typechecks, but just to be
1087 case (Map.lookup (varToString f) globalNameTable) of
1088 Just (arg_count, builder) ->
1089 if length args == arg_count then
1092 error $ "\nGenerate.genApplication(VanillaId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
1094 top <- isTopLevelBinder f
1097 -- Local binder that references a top level binding. Generate a
1098 -- component instantiation.
1099 signature <- getEntity f
1100 args' <- argsToVHDLExprs args
1101 let entity_id = ent_id signature
1102 -- TODO: Using show here isn't really pretty, but we'll need some
1103 -- unique-ish value...
1104 let label = "comp_ins_" ++ (either show prettyShow) dst
1105 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
1106 return ([mkComponentInst label entity_id portmaps], [f])
1108 -- Not a top level binder, so this must be a local variable reference.
1109 -- It should have a representable type (and thus, no arguments) and a
1110 -- signal should be generated for it. Just generate an unconditional
1112 -- FIXME : I DONT KNOW IF THE ABOVE COMMENT HOLDS HERE, SO FOR NOW JUST ERROR!
1113 -- f' <- MonadState.lift tsType $ varToVHDLExpr f
1114 -- return $ ([mkUncondAssign dst f'], [])
1115 do errtype <- case dst of
1117 htype <- MonadState.lift tsType $ mkHTypeEither (Var.varType bndr)
1119 Right vhd -> return $ show vhd
1120 error ("\nGenerate.genApplication(VanillaId): Using function from another module that is not a known builtin: " ++ (pprString f) ++ "::" ++ errtype)
1121 IdInfo.ClassOpId cls ->
1122 -- FIXME: Not looking for what instance this class op is called for
1123 -- Is quite stupid of course.
1124 case (Map.lookup (varToString f) globalNameTable) of
1125 Just (arg_count, builder) ->
1126 if length args == arg_count then
1129 error $ "\nGenerate.genApplication(ClassOpId): Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ show args
1130 Nothing -> error $ "\nGenerate.genApplication(ClassOpId): Using function from another module that is not a known builtin: " ++ pprString f
1131 details -> error $ "\nGenerate.genApplication: Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
1133 top <- isTopLevelBinder f
1136 -- Local binder that references a top level binding. Generate a
1137 -- component instantiation.
1138 signature <- getEntity f
1139 args' <- argsToVHDLExprs args
1140 let entity_id = ent_id signature
1141 -- TODO: Using show here isn't really pretty, but we'll need some
1142 -- unique-ish value...
1143 let label = "comp_ins_" ++ (either (prettyShow . varToVHDLName) prettyShow) dst
1144 let portmaps = mkAssocElems args' ((either varToVHDLName id) dst) signature
1145 return ([mkComponentInst label entity_id portmaps], [f])
1147 -- Not a top level binder, so this must be a local variable reference.
1148 -- It should have a representable type (and thus, no arguments) and a
1149 -- signal should be generated for it. Just generate an unconditional
1151 do f' <- MonadState.lift tsType $ varToVHDLExpr f
1152 return ([mkUncondAssign dst f'], [])
1153 else -- Destination has empty type, don't generate anything
1155 -----------------------------------------------------------------------------
1156 -- Functions to generate functions dealing with vectors.
1157 -----------------------------------------------------------------------------
1159 -- Returns the VHDLId of the vector function with the given name for the given
1160 -- element type. Generates -- this function if needed.
1161 vectorFunId :: Type.Type -> String -> TypeSession AST.VHDLId
1162 vectorFunId el_ty fname = do
1163 let error_msg = "\nGenerate.vectorFunId: Can not construct vector function for element: " ++ pprString el_ty
1164 -- TODO: Handle the Nothing case?
1165 elemTM_maybe <- vhdlTy error_msg el_ty
1166 let elemTM = Maybe.fromMaybe
1167 (error $ "\nGenerate.vectorFunId: Cannot generate vector function \"" ++ fname ++ "\" for the empty type \"" ++ (pprString el_ty) ++ "\"")
1169 -- TODO: This should not be duplicated from mk_vector_ty. Probably but it in
1170 -- the VHDLState or something.
1171 let vectorTM = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId elemTM)
1172 typefuns <- MonadState.get tsTypeFuns
1173 el_htype <- mkHType error_msg el_ty
1174 case Map.lookup (UVecType el_htype, fname) typefuns of
1175 -- Function already generated, just return it
1176 Just (id, _) -> return id
1177 -- Function not generated yet, generate it
1179 let functions = genUnconsVectorFuns elemTM vectorTM
1180 case lookup fname functions of
1182 MonadState.modify tsTypeFuns $ Map.insert (UVecType el_htype, fname) (function_id, (fst body))
1183 mapM_ (vectorFunId el_ty) (snd body)
1185 Nothing -> error $ "\nGenerate.vectorFunId: I don't know how to generate vector function " ++ fname
1187 function_id = mkVHDLExtId fname
1189 genUnconsVectorFuns :: AST.TypeMark -- ^ type of the vector elements
1190 -> AST.TypeMark -- ^ type of the vector
1191 -> [(String, (AST.SubProgBody, [String]))]
1192 genUnconsVectorFuns elemTM vectorTM =
1193 [ (exId, (AST.SubProgBody exSpec [] [exExpr],[]))
1194 , (replaceId, (AST.SubProgBody replaceSpec [AST.SPVD replaceVar] [replaceExpr1,replaceExpr2,replaceRet],[]))
1195 , (lastId, (AST.SubProgBody lastSpec [] [lastExpr],[]))
1196 , (initId, (AST.SubProgBody initSpec [AST.SPVD initVar] [initExpr, initRet],[]))
1197 , (minimumId, (AST.SubProgBody minimumSpec [] [minimumExpr],[]))
1198 , (takeId, (AST.SubProgBody takeSpec [AST.SPVD takeVar] [takeExpr, takeRet],[minimumId]))
1199 , (dropId, (AST.SubProgBody dropSpec [AST.SPVD dropVar] [dropExpr, dropRet],[]))
1200 , (plusgtId, (AST.SubProgBody plusgtSpec [AST.SPVD plusgtVar] [plusgtExpr, plusgtRet],[]))
1201 , (emptyId, (AST.SubProgBody emptySpec [AST.SPVD emptyVar] [emptyExpr],[]))
1202 , (singletonId, (AST.SubProgBody singletonSpec [AST.SPVD singletonVar] [singletonRet],[]))
1203 , (copynId, (AST.SubProgBody copynSpec [AST.SPVD copynVar] [copynExpr],[]))
1204 , (selId, (AST.SubProgBody selSpec [AST.SPVD selVar] [selFor, selRet],[]))
1205 , (ltplusId, (AST.SubProgBody ltplusSpec [AST.SPVD ltplusVar] [ltplusExpr, ltplusRet],[]))
1206 , (plusplusId, (AST.SubProgBody plusplusSpec [AST.SPVD plusplusVar] [plusplusExpr, plusplusRet],[]))
1207 , (lengthTId, (AST.SubProgBody lengthTSpec [] [lengthTExpr],[]))
1208 , (shiftlId, (AST.SubProgBody shiftlSpec [AST.SPVD shiftlVar] [shiftlExpr, shiftlRet], [initId]))
1209 , (shiftrId, (AST.SubProgBody shiftrSpec [AST.SPVD shiftrVar] [shiftrExpr, shiftrRet], [tailId]))
1210 , (nullId, (AST.SubProgBody nullSpec [] [nullExpr], []))
1211 , (rotlId, (AST.SubProgBody rotlSpec [AST.SPVD rotlVar] [rotlExpr, rotlRet], [nullId, lastId, initId]))
1212 , (rotrId, (AST.SubProgBody rotrSpec [AST.SPVD rotrVar] [rotrExpr, rotrRet], [nullId, tailId, headId]))
1213 , (reverseId, (AST.SubProgBody reverseSpec [AST.SPVD reverseVar] [reverseFor, reverseRet], []))
1216 ixPar = AST.unsafeVHDLBasicId "ix"
1217 vecPar = AST.unsafeVHDLBasicId "vec"
1218 vec1Par = AST.unsafeVHDLBasicId "vec1"
1219 vec2Par = AST.unsafeVHDLBasicId "vec2"
1220 nPar = AST.unsafeVHDLBasicId "n"
1221 leftPar = AST.unsafeVHDLBasicId "nLeft"
1222 rightPar = AST.unsafeVHDLBasicId "nRight"
1223 iId = AST.unsafeVHDLBasicId "i"
1225 aPar = AST.unsafeVHDLBasicId "a"
1226 fPar = AST.unsafeVHDLBasicId "f"
1227 sPar = AST.unsafeVHDLBasicId "s"
1228 resId = AST.unsafeVHDLBasicId "res"
1229 exSpec = AST.Function (mkVHDLExtId exId) [AST.IfaceVarDec vecPar vectorTM,
1230 AST.IfaceVarDec ixPar unsignedTM] elemTM
1231 exExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NIndexed
1232 (AST.IndexedName (AST.NSimple vecPar) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple ixPar)]))
1233 replaceSpec = AST.Function (mkVHDLExtId replaceId) [ AST.IfaceVarDec vecPar vectorTM
1234 , AST.IfaceVarDec iPar unsignedTM
1235 , AST.IfaceVarDec aPar elemTM
1237 -- variable res : fsvec_x (0 to vec'length-1);
1240 (AST.SubtypeIn vectorTM
1241 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1242 [AST.ToRange (AST.PrimLit "0")
1243 (AST.PrimName (AST.NAttribute $
1244 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1245 (AST.PrimLit "1")) ]))
1247 -- res AST.:= vec(0 to i-1) & a & vec(i+1 to length'vec-1)
1248 replaceExpr1 = AST.NSimple resId AST.:= AST.PrimName (AST.NSimple vecPar)
1249 replaceExpr2 = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [genExprFCall (mkVHDLBasicId toIntegerId) (AST.PrimName $ AST.NSimple iPar)]) AST.:= AST.PrimName (AST.NSimple aPar)
1250 replaceRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1251 vecSlice init last = AST.PrimName (AST.NSlice
1253 (AST.NSimple vecPar)
1254 (AST.ToRange init last)))
1255 lastSpec = AST.Function (mkVHDLExtId lastId) [AST.IfaceVarDec vecPar vectorTM] elemTM
1256 -- return vec(vec'length-1);
1257 lastExpr = AST.ReturnSm (Just (AST.PrimName $ AST.NIndexed (AST.IndexedName
1258 (AST.NSimple vecPar)
1259 [AST.PrimName (AST.NAttribute $
1260 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1261 AST.:-: AST.PrimLit "1"])))
1262 initSpec = AST.Function (mkVHDLExtId initId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1263 -- variable res : fsvec_x (0 to vec'length-2);
1266 (AST.SubtypeIn vectorTM
1267 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1268 [AST.ToRange (AST.PrimLit "0")
1269 (AST.PrimName (AST.NAttribute $
1270 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1271 (AST.PrimLit "2")) ]))
1273 -- resAST.:= vec(0 to vec'length-2)
1274 initExpr = AST.NSimple resId AST.:= (vecSlice
1276 (AST.PrimName (AST.NAttribute $
1277 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1278 AST.:-: AST.PrimLit "2"))
1279 initRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1280 minimumSpec = AST.Function (mkVHDLExtId minimumId) [AST.IfaceVarDec leftPar naturalTM,
1281 AST.IfaceVarDec rightPar naturalTM ] naturalTM
1282 minimumExpr = AST.IfSm ((AST.PrimName $ AST.NSimple leftPar) AST.:<: (AST.PrimName $ AST.NSimple rightPar))
1283 [AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple leftPar)]
1285 (Just $ AST.Else [minimumExprRet])
1286 where minimumExprRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple rightPar)
1287 takeSpec = AST.Function (mkVHDLExtId takeId) [AST.IfaceVarDec nPar naturalTM,
1288 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1289 -- variable res : fsvec_x (0 to (minimum (n,vec'length))-1);
1290 minLength = AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId minimumId))
1291 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple nPar)
1292 ,Nothing AST.:=>: AST.ADExpr (AST.PrimName (AST.NAttribute $
1293 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]
1296 (AST.SubtypeIn vectorTM
1297 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1298 [AST.ToRange (AST.PrimLit "0")
1300 (AST.PrimLit "1")) ]))
1302 -- res AST.:= vec(0 to n-1)
1303 takeExpr = AST.NSimple resId AST.:=
1304 (vecSlice (AST.PrimLit "0")
1305 (minLength AST.:-: AST.PrimLit "1"))
1306 takeRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1307 dropSpec = AST.Function (mkVHDLExtId dropId) [AST.IfaceVarDec nPar naturalTM,
1308 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1309 -- variable res : fsvec_x (0 to vec'length-n-1);
1312 (AST.SubtypeIn vectorTM
1313 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1314 [AST.ToRange (AST.PrimLit "0")
1315 (AST.PrimName (AST.NAttribute $
1316 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1317 (AST.PrimName $ AST.NSimple nPar)AST.:-: (AST.PrimLit "1")) ]))
1319 -- res AST.:= vec(n to vec'length-1)
1320 dropExpr = AST.NSimple resId AST.:= (vecSlice
1321 (AST.PrimName $ AST.NSimple nPar)
1322 (AST.PrimName (AST.NAttribute $
1323 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing)
1324 AST.:-: AST.PrimLit "1"))
1325 dropRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1326 plusgtSpec = AST.Function (mkVHDLExtId plusgtId) [AST.IfaceVarDec aPar elemTM,
1327 AST.IfaceVarDec vecPar vectorTM] vectorTM
1328 -- variable res : fsvec_x (0 to vec'length);
1331 (AST.SubtypeIn vectorTM
1332 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1333 [AST.ToRange (AST.PrimLit "0")
1334 (AST.PrimName (AST.NAttribute $
1335 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1337 plusgtExpr = AST.NSimple resId AST.:=
1338 ((AST.PrimName $ AST.NSimple aPar) AST.:&:
1339 (AST.PrimName $ AST.NSimple vecPar))
1340 plusgtRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1341 emptySpec = AST.Function (mkVHDLExtId emptyId) [] vectorTM
1344 (AST.SubtypeIn vectorTM
1345 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1346 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "-1")]))
1348 emptyExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1349 singletonSpec = AST.Function (mkVHDLExtId singletonId) [AST.IfaceVarDec aPar elemTM ]
1351 -- variable res : fsvec_x (0 to 0) := (others => a);
1354 (AST.SubtypeIn vectorTM
1355 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1356 [AST.ToRange (AST.PrimLit "0") (AST.PrimLit "0")]))
1357 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1358 (AST.PrimName $ AST.NSimple aPar)])
1359 singletonRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1360 copynSpec = AST.Function (mkVHDLExtId copynId) [AST.IfaceVarDec nPar naturalTM,
1361 AST.IfaceVarDec aPar elemTM ] vectorTM
1362 -- variable res : fsvec_x (0 to n-1) := (others => a);
1365 (AST.SubtypeIn vectorTM
1366 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1367 [AST.ToRange (AST.PrimLit "0")
1368 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1369 (AST.PrimLit "1")) ]))
1370 (Just $ AST.Aggregate [AST.ElemAssoc (Just AST.Others)
1371 (AST.PrimName $ AST.NSimple aPar)])
1373 copynExpr = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1374 selSpec = AST.Function (mkVHDLExtId selId) [AST.IfaceVarDec fPar naturalTM,
1375 AST.IfaceVarDec sPar naturalTM,
1376 AST.IfaceVarDec nPar naturalTM,
1377 AST.IfaceVarDec vecPar vectorTM ] vectorTM
1378 -- variable res : fsvec_x (0 to n-1);
1381 (AST.SubtypeIn vectorTM
1382 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1383 [AST.ToRange (AST.PrimLit "0")
1384 ((AST.PrimName (AST.NSimple nPar)) AST.:-:
1385 (AST.PrimLit "1")) ])
1388 -- for i res'range loop
1389 -- res(i) := vec(f+i*s);
1391 selFor = AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple rangeId) Nothing) [selAssign]
1392 -- res(i) := vec(f+i*s);
1393 selAssign = let origExp = AST.PrimName (AST.NSimple fPar) AST.:+:
1394 (AST.PrimName (AST.NSimple iId) AST.:*:
1395 AST.PrimName (AST.NSimple sPar)) in
1396 AST.NIndexed (AST.IndexedName (AST.NSimple resId) [AST.PrimName (AST.NSimple iId)]) AST.:=
1397 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar) [origExp]))
1399 selRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1400 ltplusSpec = AST.Function (mkVHDLExtId ltplusId) [AST.IfaceVarDec vecPar vectorTM,
1401 AST.IfaceVarDec aPar elemTM] vectorTM
1402 -- variable res : fsvec_x (0 to vec'length);
1405 (AST.SubtypeIn vectorTM
1406 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1407 [AST.ToRange (AST.PrimLit "0")
1408 (AST.PrimName (AST.NAttribute $
1409 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))]))
1411 ltplusExpr = AST.NSimple resId AST.:=
1412 ((AST.PrimName $ AST.NSimple vecPar) AST.:&:
1413 (AST.PrimName $ AST.NSimple aPar))
1414 ltplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1415 plusplusSpec = AST.Function (mkVHDLExtId plusplusId) [AST.IfaceVarDec vec1Par vectorTM,
1416 AST.IfaceVarDec vec2Par vectorTM]
1418 -- variable res : fsvec_x (0 to vec1'length + vec2'length -1);
1421 (AST.SubtypeIn vectorTM
1422 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1423 [AST.ToRange (AST.PrimLit "0")
1424 (AST.PrimName (AST.NAttribute $
1425 AST.AttribName (AST.NSimple vec1Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:+:
1426 AST.PrimName (AST.NAttribute $
1427 AST.AttribName (AST.NSimple vec2Par) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1430 plusplusExpr = AST.NSimple resId AST.:=
1431 ((AST.PrimName $ AST.NSimple vec1Par) AST.:&:
1432 (AST.PrimName $ AST.NSimple vec2Par))
1433 plusplusRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1434 lengthTSpec = AST.Function (mkVHDLExtId lengthTId) [AST.IfaceVarDec vecPar vectorTM] naturalTM
1435 lengthTExpr = AST.ReturnSm (Just $ AST.PrimName (AST.NAttribute $
1436 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing))
1437 shiftlSpec = AST.Function (mkVHDLExtId shiftlId) [AST.IfaceVarDec vecPar vectorTM,
1438 AST.IfaceVarDec aPar elemTM ] vectorTM
1439 -- variable res : fsvec_x (0 to vec'length-1);
1442 (AST.SubtypeIn vectorTM
1443 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1444 [AST.ToRange (AST.PrimLit "0")
1445 (AST.PrimName (AST.NAttribute $
1446 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1447 (AST.PrimLit "1")) ]))
1449 -- res := a & init(vec)
1450 shiftlExpr = AST.NSimple resId AST.:=
1451 (AST.PrimName (AST.NSimple aPar) AST.:&:
1452 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1453 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1454 shiftlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1455 shiftrSpec = AST.Function (mkVHDLExtId shiftrId) [AST.IfaceVarDec vecPar vectorTM,
1456 AST.IfaceVarDec aPar elemTM ] vectorTM
1457 -- variable res : fsvec_x (0 to vec'length-1);
1460 (AST.SubtypeIn vectorTM
1461 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1462 [AST.ToRange (AST.PrimLit "0")
1463 (AST.PrimName (AST.NAttribute $
1464 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1465 (AST.PrimLit "1")) ]))
1467 -- res := tail(vec) & a
1468 shiftrExpr = AST.NSimple resId AST.:=
1469 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1470 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1471 (AST.PrimName (AST.NSimple aPar)))
1473 shiftrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1474 nullSpec = AST.Function (mkVHDLExtId nullId) [AST.IfaceVarDec vecPar vectorTM] booleanTM
1475 -- return vec'length = 0
1476 nullExpr = AST.ReturnSm (Just $
1477 AST.PrimName (AST.NAttribute $
1478 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:=:
1480 rotlSpec = AST.Function (mkVHDLExtId rotlId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1481 -- variable res : fsvec_x (0 to vec'length-1);
1484 (AST.SubtypeIn vectorTM
1485 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1486 [AST.ToRange (AST.PrimLit "0")
1487 (AST.PrimName (AST.NAttribute $
1488 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1489 (AST.PrimLit "1")) ]))
1491 -- if null(vec) then res := vec else res := last(vec) & init(vec)
1492 rotlExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1493 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1494 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1496 (Just $ AST.Else [rotlExprRet])
1498 AST.NSimple resId AST.:=
1499 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId lastId))
1500 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1501 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId initId))
1502 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1503 rotlRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1504 rotrSpec = AST.Function (mkVHDLExtId rotrId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1505 -- variable res : fsvec_x (0 to vec'length-1);
1508 (AST.SubtypeIn vectorTM
1509 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1510 [AST.ToRange (AST.PrimLit "0")
1511 (AST.PrimName (AST.NAttribute $
1512 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1513 (AST.PrimLit "1")) ]))
1515 -- if null(vec) then res := vec else res := tail(vec) & head(vec)
1516 rotrExpr = AST.IfSm (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId nullId))
1517 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)])
1518 [AST.NSimple resId AST.:= (AST.PrimName $ AST.NSimple vecPar)]
1520 (Just $ AST.Else [rotrExprRet])
1522 AST.NSimple resId AST.:=
1523 ((AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId tailId))
1524 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]) AST.:&:
1525 (AST.PrimFCall $ AST.FCall (AST.NSimple (mkVHDLExtId headId))
1526 [Nothing AST.:=>: AST.ADExpr (AST.PrimName $ AST.NSimple vecPar)]))
1527 rotrRet = AST.ReturnSm (Just $ AST.PrimName $ AST.NSimple resId)
1528 reverseSpec = AST.Function (mkVHDLExtId reverseId) [AST.IfaceVarDec vecPar vectorTM] vectorTM
1531 (AST.SubtypeIn vectorTM
1532 (Just $ AST.ConstraintIndex $ AST.IndexConstraint
1533 [AST.ToRange (AST.PrimLit "0")
1534 (AST.PrimName (AST.NAttribute $
1535 AST.AttribName (AST.NSimple vecPar) (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1536 (AST.PrimLit "1")) ]))
1538 -- for i in 0 to res'range loop
1539 -- res(vec'length-i-1) := vec(i);
1542 AST.ForSM iId (AST.AttribRange $ AST.AttribName (AST.NSimple resId) (AST.NSimple rangeId) Nothing) [reverseAssign]
1543 -- res(vec'length-i-1) := vec(i);
1544 reverseAssign = AST.NIndexed (AST.IndexedName (AST.NSimple resId) [destExp]) AST.:=
1545 (AST.PrimName $ AST.NIndexed (AST.IndexedName (AST.NSimple vecPar)
1546 [AST.PrimName $ AST.NSimple iId]))
1547 where destExp = AST.PrimName (AST.NAttribute $ AST.AttribName (AST.NSimple vecPar)
1548 (AST.NSimple $ mkVHDLBasicId lengthId) Nothing) AST.:-:
1549 AST.PrimName (AST.NSimple iId) AST.:-:
1552 reverseRet = AST.ReturnSm (Just $ AST.PrimName (AST.NSimple resId))
1555 -----------------------------------------------------------------------------
1556 -- A table of builtin functions
1557 -----------------------------------------------------------------------------
1559 -- A function that generates VHDL for a builtin function
1560 type BuiltinBuilder =
1561 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
1562 -> CoreSyn.CoreBndr -- ^ The function called
1563 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
1564 -- dictionary arguments).
1565 -> TranslatorSession ([AST.ConcSm], [CoreSyn.CoreBndr])
1566 -- ^ The corresponding VHDL concurrent statements and entities
1569 -- A map of a builtin function to VHDL function builder
1570 type NameTable = Map.Map String (Int, BuiltinBuilder )
1572 -- | The builtin functions we support. Maps a name to an argument count and a
1573 -- builder function. If you add a name to this map, don't forget to add
1574 -- it to VHDL.Constants/builtinIds as well.
1575 globalNameTable :: NameTable
1576 globalNameTable = Map.fromList
1577 [ (exId , (2, genFCall True ) )
1578 , (replaceId , (3, genFCall False ) )
1579 , (headId , (1, genFCall True ) )
1580 , (lastId , (1, genFCall True ) )
1581 , (tailId , (1, genFCall False ) )
1582 , (initId , (1, genFCall False ) )
1583 , (takeId , (2, genFCall False ) )
1584 , (dropId , (2, genFCall False ) )
1585 , (selId , (4, genFCall False ) )
1586 , (plusgtId , (2, genFCall False ) )
1587 , (ltplusId , (2, genFCall False ) )
1588 , (plusplusId , (2, genFCall False ) )
1589 , (mapId , (2, genMap ) )
1590 , (zipWithId , (3, genZipWith ) )
1591 , (foldlId , (3, genFoldl ) )
1592 , (foldrId , (3, genFoldr ) )
1593 , (zipId , (2, genZip ) )
1594 , (unzipId , (1, genUnzip ) )
1595 , (shiftlId , (2, genFCall False ) )
1596 , (shiftrId , (2, genFCall False ) )
1597 , (rotlId , (1, genFCall False ) )
1598 , (rotrId , (1, genFCall False ) )
1599 , (concatId , (1, genConcat ) )
1600 , (reverseId , (1, genFCall False ) )
1601 , (iteratenId , (3, genIteraten ) )
1602 , (iterateId , (2, genIterate ) )
1603 , (generatenId , (3, genGeneraten ) )
1604 , (generateId , (2, genGenerate ) )
1605 , (emptyId , (0, genFCall False ) )
1606 , (singletonId , (1, genFCall False ) )
1607 , (copynId , (2, genFCall False ) )
1608 , (copyId , (1, genCopy ) )
1609 , (lengthTId , (1, genFCall False ) )
1610 , (nullId , (1, genFCall False ) )
1611 , (hwxorId , (2, genOperator2 AST.Xor ) )
1612 , (hwandId , (2, genOperator2 AST.And ) )
1613 , (hworId , (2, genOperator2 AST.Or ) )
1614 , (hwnotId , (1, genOperator1 AST.Not ) )
1615 , (equalityId , (2, genOperator2 (AST.:=:) ) )
1616 , (inEqualityId , (2, genOperator2 (AST.:/=:) ) )
1617 , (ltId , (2, genOperator2 (AST.:<:) ) )
1618 , (lteqId , (2, genOperator2 (AST.:<=:) ) )
1619 , (gtId , (2, genOperator2 (AST.:>:) ) )
1620 , (gteqId , (2, genOperator2 (AST.:>=:) ) )
1621 , (boolOrId , (2, genOperator2 AST.Or ) )
1622 , (boolAndId , (2, genOperator2 AST.And ) )
1623 , (boolNot , (1, genOperator1 AST.Not ) )
1624 , (plusId , (2, genOperator2 (AST.:+:) ) )
1625 , (timesId , (2, genTimes ) )
1626 , (negateId , (1, genNegation ) )
1627 , (minusId , (2, genOperator2 (AST.:-:) ) )
1628 , (fromSizedWordId , (1, genFromSizedWord ) )
1629 , (fromRangedWordId , (1, genFromRangedWord ) )
1630 , (fromIntegerId , (1, genFromInteger ) )
1631 , (resizeWordId , (1, genResize ) )
1632 , (resizeIntId , (1, genResize ) )
1633 , (sizedIntId , (1, genSizedInt ) )
1634 , (smallIntegerId , (1, genFromInteger ) )
1635 , (fstId , (1, genFst ) )
1636 , (sndId , (1, genSnd ) )
1637 , (blockRAMId , (5, genBlockRAM ) )
1638 , (splitId , (1, genSplit ) )
1639 --, (tfvecId , (1, genTFVec ) )
1640 , (minimumId , (2, error "\nFunction name: \"minimum\" is used internally, use another name"))