1 {-# LANGUAGE TemplateHaskell, DeriveDataTypeable, FlexibleContexts, TypeFamilies, TypeOperators #-}
3 module CLasH.HardwareTypes
5 , module Data.Param.TFVec
6 , module Data.RangedWord
8 , module Data.SizedWord
24 import qualified Prelude as P
25 import Prelude hiding (
26 null, length, head, tail, last, init, take, drop, (++), map, foldl, foldr,
27 zipWith, zip, unzip, concat, reverse, iterate )
29 import qualified Data.Param.TFVec as TFVec
30 import Data.Param.TFVec hiding (TFVec)
31 import Data.RangedWord
32 import qualified Data.SizedInt as SizedInt
33 import Data.SizedInt hiding (resize)
34 import qualified Data.SizedWord as SizedWord
35 import Data.SizedWord hiding (resize)
37 import Language.Haskell.TH.Lift
40 newtype State s = State s deriving (P.Show)
42 type Vector = TFVec.TFVec
44 resizeInt :: (NaturalT nT, NaturalT nT') => SizedInt nT -> SizedInt nT'
45 resizeInt = SizedInt.resize
47 resizeWord :: (NaturalT nT, NaturalT nT') => SizedWord nT -> SizedWord nT'
48 resizeWord = SizedWord.resize
52 deriving (P.Show, P.Eq, P.Read, Typeable)
56 hwand :: Bit -> Bit -> Bit
57 hwor :: Bit -> Bit -> Bit
58 hwxor :: Bit -> Bit -> Bit
61 High `hwand` High = High
68 High `hwxor` Low = High
69 Low `hwxor` High = High
75 type RAM s a = Vector (s :+: D1) a
77 type MemState s a = State (RAM s a)
82 ,((s :+: D1) :>: s) ~ True ) =>
89 blockRAM (State mem) data_in rdaddr wraddr wrenable =
90 ((State mem'), data_out)
93 -- Only write data_in to memory if write is enabled
94 mem' = if wrenable then
95 replace mem wraddr data_in