2 -- Some types used by the VHDL module.
4 {-# LANGUAGE TemplateHaskell #-}
8 import qualified Control.Monad.Trans.State as State
9 import qualified Data.Map as Map
11 import qualified Data.Accessor.Template
15 import qualified CoreSyn
18 import qualified ForSyDe.Backend.VHDL.AST as AST
24 type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
25 -- | A mapping from a haskell structure to the corresponding VHDL port
26 -- signature, or Nothing for values that do not translate to a port.
27 type VHDLSignalMap = HsValueMap VHDLSignalMapElement
29 -- A description of a VHDL entity. Contains both the entity itself as well as
30 -- info on how to map a haskell value (argument / result) on to the entity's
32 data Entity = Entity {
33 ent_id :: AST.VHDLId, -- The id of the entity
34 ent_args :: [VHDLSignalMapElement], -- A mapping of each function argument to port names
35 ent_res :: VHDLSignalMapElement -- A mapping of the function result to port names
38 -- A orderable equivalent of CoreSyn's Type for use as a map key
39 newtype OrdType = OrdType { getType :: Type.Type }
40 instance Eq OrdType where
41 (OrdType a) == (OrdType b) = Type.tcEqType a b
42 instance Ord OrdType where
43 compare (OrdType a) (OrdType b) = Type.tcCmpType a b
45 -- A map of a Core type to the corresponding type name
46 type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
48 -- A map of a vector Core type to the coressponding VHDL functions
49 type TypeFunMap = Map.Map OrdType [AST.SubProgBody]
51 -- A map of a Haskell function to a hardware signature
52 type SignatureMap = Map.Map String Entity
54 -- A map of a builtin function to VHDL function builder
55 type NameTable = Map.Map String (Int, [AST.Expr] -> AST.Expr )
57 data VHDLSession = VHDLSession {
58 -- | A map of Core type -> VHDL Type
60 -- | A map of vector Core type -> VHDL type function
61 vsTypeFuns_ :: TypeFunMap,
62 -- | A map of HsFunction -> hardware signature (entity name, port names,
64 vsSignatures_ :: SignatureMap,
65 -- | A map of Vector HsFunctions -> VHDL function call
66 vsNameTable_ :: NameTable
70 $( Data.Accessor.Template.deriveAccessors ''VHDLSession )
72 -- | The state containing a VHDL Session
73 type VHDLState = State.State VHDLSession
75 -- | A substate containing just the types
76 type TypeState = State.State TypeMap
78 -- vim: set ts=8 sw=2 sts=2 expandtab: