2 -- Some types used by the VHDL module.
4 {-# LANGUAGE TemplateHaskell #-}
8 import qualified Control.Monad.Trans.State as State
9 import qualified Data.Map as Map
11 import qualified Data.Accessor.Template
17 import qualified ForSyDe.Backend.VHDL.AST as AST
23 -- | A mapping from a haskell structure to the corresponding VHDL port
24 -- signature, or Nothing for values that do not translate to a port.
25 type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
27 -- A description of a VHDL entity. Contains both the entity itself as well as
28 -- info on how to map a haskell value (argument / result) on to the entity's
30 data Entity = Entity {
31 ent_id :: AST.VHDLId, -- The id of the entity
32 ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
33 ent_res :: VHDLSignalMap -- A mapping of the function result to port names
36 -- A orderable equivalent of CoreSyn's Type for use as a map key
37 newtype OrdType = OrdType Type.Type
38 instance Eq OrdType where
39 (OrdType a) == (OrdType b) = Type.tcEqType a b
40 instance Ord OrdType where
41 compare (OrdType a) (OrdType b) = Type.tcCmpType a b
43 -- A map of a Core type to the corresponding type name (and optionally, it's
44 -- declaration for non-primitive types).
45 type TypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDec)
47 -- A map of a Haskell function to a hardware signature
48 type SignatureMap = Map.Map HsFunction Entity
50 data VHDLSession = VHDLSession {
51 -- | A map of Core type -> VHDL Type
53 -- | A map of HsFunction -> hardware signature (entity name, port names,
55 vsSignatures_ :: SignatureMap
59 $( Data.Accessor.Template.deriveAccessors ''VHDLSession )
61 type VHDLState = State.State VHDLSession
63 -- vim: set ts=8 sw=2 sts=2 expandtab: