2 -- Some types used by the VHDL module.
6 import qualified ForSyDe.Backend.VHDL.AST as AST
11 -- | A mapping from a haskell structure to the corresponding VHDL port
12 -- signature, or Nothing for values that do not translate to a port.
13 type VHDLSignalMap = HsValueMap (Maybe (AST.VHDLId, AST.TypeMark))
15 -- A description of a VHDL entity. Contains both the entity itself as well as
16 -- info on how to map a haskell value (argument / result) on to the entity's
18 data Entity = Entity {
19 ent_id :: AST.VHDLId, -- The id of the entity
20 ent_args :: [VHDLSignalMap], -- A mapping of each function argument to port names
21 ent_res :: VHDLSignalMap, -- A mapping of the function result to port names
22 ent_decl :: Maybe AST.EntityDec, -- The actual entity declaration. Can be empty for builtin functions.
23 ent_pkg_decl :: Maybe AST.PackageDec -- A package declaration with types for this entity