2 -- Some types used by the VHDL module.
4 {-# LANGUAGE TemplateHaskell #-}
8 import qualified Control.Monad.Trans.State as State
9 import qualified Data.Map as Map
11 import qualified Data.Accessor.Template
15 import qualified CoreSyn
18 import qualified ForSyDe.Backend.VHDL.AST as AST
24 type VHDLSignalMapElement = (Maybe (AST.VHDLId, AST.TypeMark))
25 -- | A mapping from a haskell structure to the corresponding VHDL port
26 -- signature, or Nothing for values that do not translate to a port.
27 type VHDLSignalMap = HsValueMap VHDLSignalMapElement
29 -- A description of a VHDL entity. Contains both the entity itself as well as
30 -- info on how to map a haskell value (argument / result) on to the entity's
32 data Entity = Entity {
33 ent_id :: AST.VHDLId, -- The id of the entity
34 ent_args :: [VHDLSignalMapElement], -- A mapping of each function argument to port names
35 ent_res :: VHDLSignalMapElement -- A mapping of the function result to port names
38 -- A orderable equivalent of CoreSyn's Type for use as a map key
39 newtype OrdType = OrdType { getType :: Type.Type }
40 instance Eq OrdType where
41 (OrdType a) == (OrdType b) = Type.tcEqType a b
42 instance Ord OrdType where
43 compare (OrdType a) (OrdType b) = Type.tcCmpType a b
45 -- A map of a Core type to the corresponding type name
46 type TypeMap = Map.Map OrdType (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn)
48 -- A map of Elem types to the corresponding VHDL Id for the Vector
49 type ElemTypeMap = Map.Map OrdType (AST.VHDLId, AST.TypeDef)
51 -- A map of a vector Core element type and function name to the coressponding
52 -- VHDLId of the function and the function body.
53 type TypeFunMap = Map.Map (OrdType, String) (AST.VHDLId, AST.SubProgBody)
55 -- A map of a Haskell function to a hardware signature
56 type SignatureMap = Map.Map CoreSyn.CoreBndr Entity
58 data VHDLState = VHDLState {
59 -- | A map of Core type -> VHDL Type
61 -- | A map of Elem types -> VHDL Vector Id
62 vsElemTypes_ :: ElemTypeMap,
63 -- | A map of vector Core type -> VHDL type function
64 vsTypeFuns_ :: TypeFunMap,
65 -- | A map of HsFunction -> hardware signature (entity name, port names,
67 vsSignatures_ :: SignatureMap
71 $( Data.Accessor.Template.deriveAccessors ''VHDLState )
73 -- | The state containing a VHDL Session
74 type VHDLSession = State.State VHDLState
76 -- | A substate containing just the types
77 type TypeState = State.State TypeMap
79 -- A function that generates VHDL for a builtin function
81 (Either CoreSyn.CoreBndr AST.VHDLName) -- ^ The destination signal and it's original type
82 -> CoreSyn.CoreBndr -- ^ The function called
83 -> [Either CoreSyn.CoreExpr AST.Expr] -- ^ The value arguments passed (excluding type and
84 -- dictionary arguments).
85 -> VHDLSession [AST.ConcSm] -- ^ The resulting concurrent statements.
87 -- A map of a builtin function to VHDL function builder
88 type NameTable = Map.Map String (Int, BuiltinBuilder )
90 -- vim: set ts=8 sw=2 sts=2 expandtab: