2 -- Functions to generate VHDL from FlatFunctions
7 import qualified Data.Foldable as Foldable
8 import qualified Data.List as List
9 import qualified Data.Map as Map
10 import qualified Maybe
11 import qualified Control.Monad as Monad
12 import qualified Control.Arrow as Arrow
13 import qualified Control.Monad.Trans.State as State
14 import qualified Data.Traversable as Traversable
15 import qualified Data.Monoid as Monoid
17 import qualified Data.Accessor.MonadState as MonadState
18 import Text.Regex.Posix
22 import qualified ForSyDe.Backend.VHDL.AST as AST
28 import qualified OccName
31 import qualified IdInfo
32 import qualified TyCon
33 import qualified TcType
34 import qualified DataCon
35 import qualified CoreSubst
36 import qualified CoreUtils
37 import Outputable ( showSDoc, ppr )
43 import TranslatorTypes
49 import GlobalNameTable
52 [(CoreSyn.CoreBndr, CoreSyn.CoreExpr)]
53 -> [(AST.VHDLId, AST.DesignFile)]
55 createDesignFiles binds =
56 (mkVHDLBasicId "types", AST.DesignFile ieee_context [type_package_dec, type_package_body]) :
57 map (Arrow.second $ AST.DesignFile full_context) units
60 init_session = VHDLSession Map.empty Map.empty Map.empty Map.empty globalNameTable
61 (units, final_session) =
62 State.runState (createLibraryUnits binds) init_session
63 tyfun_decls = Map.elems (final_session ^.vsTypeFuns)
64 ty_decls = map mktydecl $ Map.elems (final_session ^. vsTypes)
65 vec_decls = map (\(v_id, v_def) -> AST.PDITD $ AST.TypeDec v_id v_def) (Map.elems (final_session ^. vsElemTypes))
66 tfvec_index_decl = AST.PDISD $ AST.SubtypeDec tfvec_indexTM tfvec_index_def
67 tfvec_range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit "-1") (AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerTM) highId Nothing)
68 tfvec_index_def = AST.SubtypeIn integerTM (Just tfvec_range)
70 AST.Library $ mkVHDLBasicId "IEEE",
71 mkUseAll ["IEEE", "std_logic_1164"],
72 mkUseAll ["IEEE", "numeric_std"]
75 mkUseAll ["work", "types"]
77 type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ vec_decls ++ ty_decls ++ subProgSpecs)
78 type_package_body = AST.LUPackageBody $ AST.PackageBody typesId (concat tyfun_decls)
79 subProgSpecs = concat (map subProgSpec tyfun_decls)
80 subProgSpec = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec)
81 mktydecl :: (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn) -> AST.PackageDecItem
82 mktydecl (ty_id, Left ty_def) = AST.PDITD $ AST.TypeDec ty_id ty_def
83 mktydecl (ty_id, Right ty_def) = AST.PDISD $ AST.SubtypeDec ty_id ty_def
85 -- Create a use foo.bar.all statement. Takes a list of components in the used
86 -- name. Must contain at least two components
87 mkUseAll :: [String] -> AST.ContextItem
89 AST.Use $ from AST.:.: AST.All
91 base_prefix = (AST.NSimple $ mkVHDLBasicId $ head ss)
92 from = foldl select base_prefix (tail ss)
93 select prefix s = AST.NSelected $ prefix AST.:.: (AST.SSimple $ mkVHDLBasicId s)
96 [(CoreSyn.CoreBndr, CoreSyn.CoreExpr)]
97 -> VHDLState [(AST.VHDLId, [AST.LibraryUnit])]
99 createLibraryUnits binds = do
100 entities <- Monad.mapM createEntity binds
101 archs <- Monad.mapM createArchitecture binds
104 let AST.EntityDec id _ = ent in
105 (id, [AST.LUEntity ent, AST.LUArch arch])
109 -- | Create an entity for a given function
111 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- | The function
112 -> VHDLState AST.EntityDec -- | The resulting entity
114 createEntity (fname, expr) = do
115 -- Strip off lambda's, these will be arguments
116 let (args, letexpr) = CoreSyn.collectBinders expr
117 args' <- Monad.mapM mkMap args
118 -- There must be a let at top level
119 let (CoreSyn.Let binds (CoreSyn.Var res)) = letexpr
121 let vhdl_id = mkVHDLBasicId $ bndrToString fname ++ "_" ++ varToStringUniq fname
122 let ent_decl' = createEntityAST vhdl_id args' res'
123 let AST.EntityDec entity_id _ = ent_decl'
124 let signature = Entity entity_id args' res'
125 modA vsSignatures (Map.insert fname signature)
129 --[(SignalId, SignalInfo)]
131 -> VHDLState VHDLSignalMapElement
132 -- We only need the vsTypes element from the state
135 --info = Maybe.fromMaybe
136 -- (error $ "Signal not found in the name map? This should not happen!")
137 -- (lookup id sigmap)
138 -- Assume the bndr has a valid VHDL id already
139 id = bndrToVHDLId bndr
140 ty = Var.varType bndr
142 if True -- isPortSigUse $ sigUse info
144 type_mark <- vhdl_ty ty
145 return $ Just (id, type_mark)
150 -- | Create the VHDL AST for an entity
152 AST.VHDLId -- | The name of the function
153 -> [VHDLSignalMapElement] -- | The entity's arguments
154 -> VHDLSignalMapElement -- | The entity's result
155 -> AST.EntityDec -- | The entity with the ent_decl filled in as well
157 createEntityAST vhdl_id args res =
158 AST.EntityDec vhdl_id ports
160 -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
161 ports = Maybe.catMaybes $
162 map (mkIfaceSigDec AST.In) args
163 ++ [mkIfaceSigDec AST.Out res]
165 -- Add a clk port if we have state
166 clk_port = if True -- hasState hsfunc
168 Just $ AST.IfaceSigDec (mkVHDLExtId "clk") AST.In VHDL.std_logic_ty
172 -- | Create a port declaration
174 AST.Mode -- | The mode for the port (In / Out)
175 -> Maybe (AST.VHDLId, AST.TypeMark) -- | The id and type for the port
176 -> Maybe AST.IfaceSigDec -- | The resulting port declaration
178 mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty
179 mkIfaceSigDec _ Nothing = Nothing
181 -- | Generate a VHDL entity name for the given hsfunc
183 -- TODO: This doesn't work for functions with multiple signatures!
184 -- Use a Basic Id, since using extended id's for entities throws off
185 -- precision and causes problems when generating filenames.
186 mkVHDLBasicId $ hsFuncName hsfunc
188 -- | Create an architecture for a given function
189 createArchitecture ::
190 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The function
191 -> VHDLState AST.ArchBody -- ^ The architecture for this function
193 createArchitecture (fname, expr) = do
194 signaturemap <- getA vsSignatures
195 let signature = Maybe.fromMaybe
196 (error $ "Generating architecture for function " ++ (pprString fname) ++ "without signature? This should not happen!")
197 (Map.lookup fname signaturemap)
198 let entity_id = ent_id signature
199 -- Strip off lambda's, these will be arguments
200 let (args, letexpr) = CoreSyn.collectBinders expr
201 -- There must be a let at top level
202 let (CoreSyn.Let (CoreSyn.Rec binds) (Var res)) = letexpr
204 -- Create signal declarations for all binders in the let expression, except
205 -- for the output port (that will already have an output port declared in
207 sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds)
208 let sig_decs = Maybe.catMaybes $ sig_dec_maybes
210 statementss <- Monad.mapM mkConcSm binds
211 let statements = concat statementss
212 return $ AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
214 procs = map mkStateProcSm [] -- (makeStatePairs flatfunc)
215 procs' = map AST.CSPSm procs
216 -- mkSigDec only uses vsTypes from the state
219 -- | Looks up all pairs of old state, new state signals, together with
220 -- the state id they represent.
221 makeStatePairs :: FlatFunction -> [(StateId, SignalInfo, SignalInfo)]
222 makeStatePairs flatfunc =
223 [(Maybe.fromJust $ oldStateId $ sigUse old_info, old_info, new_info)
224 | old_info <- map snd (flat_sigs flatfunc)
225 , new_info <- map snd (flat_sigs flatfunc)
226 -- old_info must be an old state (and, because of the next equality,
227 -- new_info must be a new state).
228 , Maybe.isJust $ oldStateId $ sigUse old_info
229 -- And the state numbers must match
230 , (oldStateId $ sigUse old_info) == (newStateId $ sigUse new_info)]
232 -- Replace the second tuple element with the corresponding SignalInfo
233 --args_states = map (Arrow.second $ signalInfo sigs) args
234 mkStateProcSm :: (StateId, SignalInfo, SignalInfo) -> AST.ProcSm
235 mkStateProcSm (num, old, new) =
236 AST.ProcSm label [clk] [statement]
238 label = mkVHDLExtId $ "state_" ++ (show num)
239 clk = mkVHDLExtId "clk"
240 rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
241 wform = AST.Wform [AST.WformElem (AST.PrimName $ AST.NSimple $ getSignalId new) Nothing]
242 assign = AST.SigAssign (AST.NSimple $ getSignalId old) wform
243 rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
244 statement = AST.IfSm rising_edge_clk [assign] [] Nothing
246 mkSigDec :: CoreSyn.CoreBndr -> VHDLState (Maybe AST.SigDec)
248 if True then do --isInternalSigUse use || isStateSigUse use then do
249 type_mark <- vhdl_ty $ Var.varType bndr
250 return $ Just (AST.SigDec (bndrToVHDLId bndr) type_mark Nothing)
254 -- | Creates a VHDL Id from a named SignalInfo. Errors out if the SignalInfo
256 getSignalId :: SignalInfo -> AST.VHDLId
258 mkVHDLExtId $ Maybe.fromMaybe
259 (error $ "Unnamed signal? This should not happen!")
262 -- | Transforms a core binding into a VHDL concurrent statement
264 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
265 -> VHDLState [AST.ConcSm] -- ^ The corresponding VHDL component instantiations.
267 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
268 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
269 let valargs' = filter isValArg args
270 let valargs = filter (\(CoreSyn.Var bndr) -> not (Id.isDictId bndr)) valargs'
271 case Var.globalIdVarDetails f of
272 IdInfo.DataConWorkId dc ->
273 -- It's a datacon. Create a record from its arguments.
274 -- First, filter out type args. TODO: Is this the best way to do this?
275 -- The types should already have been taken into acocunt when creating
276 -- the signal, so this should probably work...
277 --let valargs = filter isValArg args in
278 if all is_var valargs then do
279 labels <- getFieldLabels (CoreUtils.exprType app)
280 return $ zipWith mkassign labels valargs
282 error $ "VHDL.mkConcSm Not in normal form: One ore more complex arguments: " ++ pprString args
284 mkassign :: AST.VHDLId -> CoreExpr -> AST.ConcSm
285 mkassign label (Var arg) =
286 let sel_name = mkSelectedName bndr label in
287 mkUncondAssign (Right sel_name) (varToVHDLExpr arg)
288 IdInfo.VanillaGlobal -> do
289 -- It's a global value imported from elsewhere. These can be builtin
291 funSignatures <- getA vsNameTable
292 entSignatures <- getA vsSignatures
293 case (Map.lookup (bndrToString f) funSignatures) of
294 Just (arg_count, builder) ->
295 if length valargs == arg_count then
299 sigs = map (bndrToString.varBndr) valargs
300 sigsNames = map (\signal -> (AST.PrimName (AST.NSimple (mkVHDLExtId signal)))) sigs
301 func = funBuilder sigsNames
302 src_wform = AST.Wform [AST.WformElem func Nothing]
303 dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
304 assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
306 return [AST.CSSASm assign]
309 sigs = map (varBndr) valargs
310 signature = Maybe.fromMaybe
311 (error $ "Using function '" ++ (bndrToString (head sigs)) ++ "' without signature? This should not happen!")
312 (Map.lookup (head sigs) entSignatures)
313 arg_name = mkVHDLExtId (bndrToString (last sigs))
314 dst_name = mkVHDLExtId (bndrToString bndr)
315 genSm = genBuilder 4 signature [arg_name, dst_name]
316 in return [AST.CSGSm genSm]
318 error $ "VHDL.mkConcSm Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ pprString valargs
319 Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
320 IdInfo.NotGlobalId -> do
321 signatures <- getA vsSignatures
322 -- This is a local id, so it should be a function whose definition we
323 -- have and which can be turned into a component instantiation.
325 signature = Maybe.fromMaybe
326 (error $ "Using function '" ++ (bndrToString f) ++ "' without signature? This should not happen!")
327 (Map.lookup f signatures)
328 entity_id = ent_id signature
329 label = "comp_ins_" ++ bndrToString bndr
330 -- Add a clk port if we have state
331 --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
332 clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
333 --portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else [])
334 portmaps = clk_port : mkAssocElems args bndr signature
336 return [AST.CSISm $ AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)]
337 details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
339 -- A single alt case must be a selector. This means thee scrutinee is a simple
340 -- variable, the alternative is a dataalt with a single non-wild binder that
342 mkConcSm (bndr, expr@(Case (Var scrut) b ty [alt])) =
344 (DataAlt dc, bndrs, (Var sel_bndr)) -> do
345 case List.elemIndex sel_bndr bndrs of
347 labels <- getFieldLabels (Id.idType scrut)
348 let label = labels!!i
349 let sel_name = mkSelectedName scrut label
350 let sel_expr = AST.PrimName sel_name
351 return [mkUncondAssign (Left bndr) sel_expr]
352 Nothing -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
354 _ -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
356 -- Multiple case alt are be conditional assignments and have only wild
357 -- binders in the alts and only variables in the case values and a variable
358 -- for a scrutinee. We check the constructor of the second alt, since the
359 -- first is the default case, if there is any.
360 mkConcSm (bndr, (Case (Var scrut) b ty [(_, _, Var false), (con, _, Var true)])) =
362 cond_expr = (varToVHDLExpr scrut) AST.:=: (conToVHDLExpr con)
363 true_expr = (varToVHDLExpr true)
364 false_expr = (varToVHDLExpr false)
366 return [mkCondAssign (Left bndr) cond_expr true_expr false_expr]
367 mkConcSm (_, (Case (Var _) _ _ alts)) = error "VHDL.mkConcSm Not in normal form: Case statement with more than two alternatives"
368 mkConcSm (_, Case _ _ _ _) = error "VHDL.mkConcSm Not in normal form: Case statement has does not have a simple variable as scrutinee"
369 mkConcSm (bndr, expr) = error $ "VHDL.mkConcSM Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
371 -- Create an unconditional assignment statement
373 Either CoreBndr AST.VHDLName -- ^ The signal to assign to
374 -> AST.Expr -- ^ The expression to assign
375 -> AST.ConcSm -- ^ The resulting concurrent statement
376 mkUncondAssign dst expr = mkAssign dst Nothing expr
378 -- Create a conditional assignment statement
380 Either CoreBndr AST.VHDLName -- ^ The signal to assign to
381 -> AST.Expr -- ^ The condition
382 -> AST.Expr -- ^ The value when true
383 -> AST.Expr -- ^ The value when false
384 -> AST.ConcSm -- ^ The resulting concurrent statement
385 mkCondAssign dst cond true false = mkAssign dst (Just (cond, true)) false
387 -- Create a conditional or unconditional assignment statement
389 Either CoreBndr AST.VHDLName -> -- ^ The signal to assign to
390 Maybe (AST.Expr , AST.Expr) -> -- ^ Optionally, the condition to test for
391 -- and the value to assign when true.
392 AST.Expr -> -- ^ The value to assign when false or no condition
393 AST.ConcSm -- ^ The resulting concurrent statement
395 mkAssign dst cond false_expr =
397 -- I'm not 100% how this assignment AST works, but this gets us what we
399 whenelse = case cond of
400 Just (cond_expr, true_expr) ->
402 true_wform = AST.Wform [AST.WformElem true_expr Nothing]
404 [AST.WhenElse true_wform cond_expr]
406 false_wform = AST.Wform [AST.WformElem false_expr Nothing]
407 dst_name = case dst of
408 Left bndr -> AST.NSimple (bndrToVHDLId bndr)
410 assign = dst_name AST.:<==: (AST.ConWforms whenelse false_wform Nothing)
414 -- Create a record field selector that selects the given label from the record
415 -- stored in the given binder.
416 mkSelectedName :: CoreBndr -> AST.VHDLId -> AST.VHDLName
417 mkSelectedName bndr label =
419 sel_prefix = AST.NSimple $ bndrToVHDLId bndr
420 sel_suffix = AST.SSimple $ label
422 AST.NSelected $ sel_prefix AST.:.: sel_suffix
424 -- Finds the field labels for VHDL type generated for the given Core type,
425 -- which must result in a record type.
426 getFieldLabels :: Type.Type -> VHDLState [AST.VHDLId]
427 getFieldLabels ty = do
428 -- Ensure that the type is generated (but throw away it's VHDLId)
430 -- Get the types map, lookup and unpack the VHDL TypeDef
431 types <- getA vsTypes
432 case Map.lookup (OrdType ty) types of
433 Just (_, Left (AST.TDR (AST.RecordTypeDef elems))) -> return $ map (\(AST.ElementDec id _) -> id) elems
434 _ -> error $ "VHDL.getFieldLabels Type not found or not a record type? This should not happen! Type: " ++ (show ty)
436 -- Turn a variable reference into a AST expression
437 varToVHDLExpr :: Var.Var -> AST.Expr
438 varToVHDLExpr var = AST.PrimName $ AST.NSimple $ bndrToVHDLId var
440 -- Turn a constructor into an AST expression. For dataconstructors, this is
441 -- only the constructor itself, not any arguments it has. Should not be called
442 -- with a DEFAULT constructor.
443 conToVHDLExpr :: CoreSyn.AltCon -> AST.Expr
444 conToVHDLExpr (DataAlt dc) = AST.PrimLit lit
446 tycon = DataCon.dataConTyCon dc
447 tyname = TyCon.tyConName tycon
448 dcname = DataCon.dataConName dc
449 lit = case Name.getOccString tyname of
450 -- TODO: Do something more robust than string matching
451 "Bit" -> case Name.getOccString dcname of "High" -> "'1'"; "Low" -> "'0'"
452 "Bool" -> case Name.getOccString dcname of "True" -> "true"; "False" -> "false"
453 conToVHDLExpr (LitAlt _) = error "VHDL.conToVHDLExpr Literals not support in case alternatives yet"
454 conToVHDLExpr DEFAULT = error "VHDL.conToVHDLExpr DEFAULT alternative should not occur here!"
459 mkConcSm sigs (UncondDef src dst) _ = do
460 src_expr <- vhdl_expr src
461 let src_wform = AST.Wform [AST.WformElem src_expr Nothing]
462 let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
463 let assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
464 return $ AST.CSSASm assign
466 vhdl_expr (Left id) = return $ mkIdExpr sigs id
467 vhdl_expr (Right expr) =
470 return $ (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
471 (Literal lit Nothing) ->
472 return $ AST.PrimLit lit
473 (Literal lit (Just ty)) -> do
474 -- Create a cast expression, which is just a function call using the
475 -- type name as the function name.
476 let litexpr = AST.PrimLit lit
478 let ty_name = AST.NSimple ty_id
479 let args = [Nothing AST.:=>: (AST.ADExpr litexpr)]
480 return $ AST.PrimFCall $ AST.FCall ty_name args
482 return $ (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
484 mkConcSm sigs (CondDef cond true false dst) _ =
486 cond_expr = mkIdExpr sigs cond
487 true_expr = mkIdExpr sigs true
488 false_expr = mkIdExpr sigs false
489 false_wform = AST.Wform [AST.WformElem false_expr Nothing]
490 true_wform = AST.Wform [AST.WformElem true_expr Nothing]
491 whenelse = AST.WhenElse true_wform cond_expr
492 dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
493 assign = dst_name AST.:<==: (AST.ConWforms [whenelse] false_wform Nothing)
495 return $ AST.CSSASm assign
497 -- | Turn a SignalId into a VHDL Expr
498 mkIdExpr :: [(SignalId, SignalInfo)] -> SignalId -> AST.Expr
500 let src_name = AST.NSimple (getSignalId $ signalInfo sigs id) in
501 AST.PrimName src_name
504 [CoreSyn.CoreExpr] -- | The argument that are applied to function
505 -> CoreSyn.CoreBndr -- | The binder in which to store the result
506 -> Entity -- | The entity to map against.
507 -> [AST.AssocElem] -- | The resulting port maps
509 mkAssocElems args res entity =
510 -- Create the actual AssocElems
511 Maybe.catMaybes $ zipWith mkAssocElem ports sigs
513 -- Turn the ports and signals from a map into a flat list. This works,
514 -- since the maps must have an identical form by definition. TODO: Check
516 arg_ports = ent_args entity
517 res_port = ent_res entity
518 -- Extract the id part from the (id, type) tuple
519 ports = map (Monad.liftM fst) (res_port : arg_ports)
520 -- Translate signal numbers into names
521 sigs = (bndrToString res : map (bndrToString.varBndr) args)
523 -- Turns a Var CoreExpr into the Id inside it. Will of course only work for
524 -- simple Var CoreExprs, not complexer ones.
525 varBndr :: CoreSyn.CoreExpr -> Var.Id
526 varBndr (CoreSyn.Var id) = id
528 -- | Look up a signal in the signal name map
529 lookupSigName :: [(SignalId, SignalInfo)] -> SignalId -> String
530 lookupSigName sigs sig = name
532 info = Maybe.fromMaybe
533 (error $ "Unknown signal " ++ (show sig) ++ " used? This should not happen!")
535 name = Maybe.fromMaybe
536 (error $ "Unnamed signal " ++ (show sig) ++ " used? This should not happen!")
539 -- | Create an VHDL port -> signal association
540 mkAssocElem :: Maybe AST.VHDLId -> String -> Maybe AST.AssocElem
541 mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLExtId signal)))
542 mkAssocElem Nothing _ = Nothing
544 -- | The VHDL Bit type
545 bit_ty :: AST.TypeMark
546 bit_ty = AST.unsafeVHDLBasicId "Bit"
548 -- | The VHDL Boolean type
549 bool_ty :: AST.TypeMark
550 bool_ty = AST.unsafeVHDLBasicId "Boolean"
552 -- | The VHDL std_logic
553 std_logic_ty :: AST.TypeMark
554 std_logic_ty = AST.unsafeVHDLBasicId "std_logic"
556 -- Translate a Haskell type to a VHDL type
557 vhdl_ty :: Type.Type -> VHDLState AST.TypeMark
559 typemap <- getA vsTypes
560 let builtin_ty = do -- See if this is a tycon and lookup its name
561 (tycon, args) <- Type.splitTyConApp_maybe ty
562 let name = Name.getOccString (TyCon.tyConName tycon)
563 Map.lookup name builtin_types
564 -- If not a builtin type, try the custom types
565 let existing_ty = (fmap fst) $ Map.lookup (OrdType ty) typemap
566 case Monoid.getFirst $ Monoid.mconcat (map Monoid.First [builtin_ty, existing_ty]) of
567 -- Found a type, return it
569 -- No type yet, try to construct it
571 newty_maybe <- (construct_vhdl_ty ty)
573 Just (ty_id, ty_def) -> do
574 -- TODO: Check name uniqueness
575 modA vsTypes (Map.insert (OrdType ty) (ty_id, ty_def))
577 Nothing -> error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty)
579 -- Construct a new VHDL type for the given Haskell type.
580 construct_vhdl_ty :: Type.Type -> VHDLState (Maybe (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn))
581 construct_vhdl_ty ty = do
582 case Type.splitTyConApp_maybe ty of
583 Just (tycon, args) -> do
584 let name = Name.getOccString (TyCon.tyConName tycon)
587 res <- mk_vector_ty (tfvec_len ty) (tfvec_elem ty)
588 return $ Just $ (Arrow.second Right) res
590 -- res <- mk_vector_ty (sized_word_len ty) ty
591 -- return $ Just $ (Arrow.second Left) res
593 res <- mk_natural_ty 0 (ranged_word_bound ty)
594 return $ Just $ (Arrow.second Right) res
595 -- Create a custom type from this tycon
596 otherwise -> mk_tycon_ty tycon args
597 Nothing -> return $ Nothing
599 -- | Create VHDL type for a custom tycon
600 mk_tycon_ty :: TyCon.TyCon -> [Type.Type] -> VHDLState (Maybe (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn))
601 mk_tycon_ty tycon args =
602 case TyCon.tyConDataCons tycon of
603 -- Not an algebraic type
604 [] -> error $ "Only custom algebraic types are supported: " ++ (showSDoc $ ppr tycon)
606 let arg_tys = DataCon.dataConRepArgTys dc
607 -- TODO: CoreSubst docs say each Subs can be applied only once. Is this a
608 -- violation? Or does it only mean not to apply it again to the same
610 let real_arg_tys = map (CoreSubst.substTy subst) arg_tys
611 elem_tys <- mapM vhdl_ty real_arg_tys
612 let elems = zipWith AST.ElementDec recordlabels elem_tys
613 -- For a single construct datatype, build a record with one field for
615 -- TODO: Add argument type ids to this, to ensure uniqueness
616 -- TODO: Special handling for tuples?
617 let ty_id = mkVHDLExtId $ nameToString (TyCon.tyConName tycon)
618 let ty_def = AST.TDR $ AST.RecordTypeDef elems
619 return $ Just (ty_id, Left ty_def)
620 dcs -> error $ "Only single constructor datatypes supported: " ++ (showSDoc $ ppr tycon)
622 -- Create a subst that instantiates all types passed to the tycon
623 -- TODO: I'm not 100% sure that this is the right way to do this. It seems
624 -- to work so far, though..
625 tyvars = TyCon.tyConTyVars tycon
626 subst = CoreSubst.extendTvSubstList CoreSubst.emptySubst (zip tyvars args)
628 -- | Create a VHDL vector type
630 Int -- ^ The length of the vector
631 -> Type.Type -- ^ The Haskell element type of the Vector
632 -> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created.
634 mk_vector_ty len el_ty = do
635 elem_types_map <- getA vsElemTypes
636 el_ty_tm <- vhdl_ty el_ty
637 let ty_id = mkVHDLExtId $ "vector-"++ (AST.fromVHDLId el_ty_tm) ++ "-0_to_" ++ (show len)
638 let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
639 let existing_elem_ty = (fmap fst) $ Map.lookup (OrdType el_ty) elem_types_map
640 case existing_elem_ty of
642 let ty_def = AST.SubtypeIn t (Just range)
643 return (ty_id, ty_def)
645 let vec_id = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId el_ty_tm)
646 let vec_def = AST.TDA $ AST.UnconsArrayDef [tfvec_indexTM] el_ty_tm
647 modA vsElemTypes (Map.insert (OrdType el_ty) (vec_id, vec_def))
648 modA vsTypeFuns (Map.insert (OrdType el_ty) (genUnconsVectorFuns el_ty_tm vec_id))
649 let ty_def = AST.SubtypeIn vec_id (Just range)
650 return (ty_id, ty_def)
653 Int -- ^ The minimum bound (> 0)
654 -> Int -- ^ The maximum bound (> minimum bound)
655 -> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created.
656 mk_natural_ty min_bound max_bound = do
657 let ty_id = mkVHDLExtId $ "nat_" ++ (show min_bound) ++ "_to_" ++ (show max_bound)
658 let range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit $ (show min_bound)) (AST.PrimLit $ (show max_bound))
659 let ty_def = AST.SubtypeIn naturalTM (Just range)
660 return (ty_id, ty_def)
664 ("Bit", std_logic_ty),
665 ("Bool", bool_ty) -- TysWiredIn.boolTy
669 -- Can only contain alphanumerics and underscores. The supplied string must be
670 -- a valid basic id, otherwise an error value is returned. This function is
671 -- not meant to be passed identifiers from a source file, use mkVHDLExtId for
673 mkVHDLBasicId :: String -> AST.VHDLId
675 AST.unsafeVHDLBasicId $ (strip_multiscore . strip_leading . strip_invalid) s
677 -- Strip invalid characters.
678 strip_invalid = filter (`elem` ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ "_.")
679 -- Strip leading numbers and underscores
680 strip_leading = dropWhile (`elem` ['0'..'9'] ++ "_")
681 -- Strip multiple adjacent underscores
682 strip_multiscore = concat . map (\cs ->
688 -- Shortcut for Extended VHDL Id's. These Id's can contain a lot more
689 -- different characters than basic ids, but can never be used to refer to
691 -- Use extended Ids for any values that are taken from the source file.
692 mkVHDLExtId :: String -> AST.VHDLId
694 AST.unsafeVHDLExtId $ strip_invalid s
696 -- Allowed characters, taken from ForSyde's mkVHDLExtId
697 allowed = ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ " \"#&\\'()*+,./:;<=>_|!$%@?[]^`{}~-"
698 strip_invalid = filter (`elem` allowed)
700 -- Creates a VHDL Id from a binder
705 bndrToVHDLId = mkVHDLExtId . OccName.occNameString . Name.nameOccName . Var.varName
707 -- Extracts the binder name as a String
711 bndrToString = OccName.occNameString . Name.nameOccName . Var.varName
713 -- Get the string version a Var's unique
714 varToStringUniq = show . Var.varUnique
716 -- Extracts the string version of the name
717 nameToString :: Name.Name -> String
718 nameToString = OccName.occNameString . Name.nameOccName
720 recordlabels = map (\c -> mkVHDLBasicId [c]) ['A'..'Z']
722 -- | Map a port specification of a builtin function to a VHDL Signal to put in
724 toVHDLSignalMapElement :: (String, AST.TypeMark) -> VHDLSignalMapElement
725 toVHDLSignalMapElement (name, ty) = Just (mkVHDLBasicId name, ty)