2 -- Functions to generate VHDL from FlatFunctions
7 import qualified Data.Foldable as Foldable
8 import qualified Data.List as List
9 import qualified Data.Map as Map
10 import qualified Maybe
11 import qualified Control.Monad as Monad
12 import qualified Control.Arrow as Arrow
13 import qualified Control.Monad.Trans.State as State
14 import qualified Data.Traversable as Traversable
15 import qualified Data.Monoid as Monoid
17 import qualified Data.Accessor.MonadState as MonadState
18 import Text.Regex.Posix
22 import qualified ForSyDe.Backend.VHDL.AST as AST
28 import qualified OccName
31 import qualified IdInfo
32 import qualified TyCon
33 import qualified TcType
34 import qualified DataCon
35 import qualified CoreSubst
36 import qualified CoreUtils
37 import Outputable ( showSDoc, ppr )
43 import TranslatorTypes
49 import GlobalNameTable
52 [(CoreSyn.CoreBndr, CoreSyn.CoreExpr)]
53 -> [(AST.VHDLId, AST.DesignFile)]
55 createDesignFiles binds =
56 (mkVHDLBasicId "types", AST.DesignFile ieee_context [type_package_dec, type_package_body]) :
57 map (Arrow.second $ AST.DesignFile full_context) units
60 init_session = VHDLSession Map.empty Map.empty Map.empty Map.empty globalNameTable
61 (units, final_session) =
62 State.runState (createLibraryUnits binds) init_session
63 tyfun_decls = Map.elems (final_session ^.vsTypeFuns)
64 ty_decls = map mktydecl $ Map.elems (final_session ^. vsTypes)
65 vec_decls = map (\(v_id, v_def) -> AST.PDITD $ AST.TypeDec v_id v_def) (Map.elems (final_session ^. vsElemTypes))
66 tfvec_index_decl = AST.PDISD $ AST.SubtypeDec tfvec_indexTM tfvec_index_def
67 tfvec_range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit "-1") (AST.PrimName $ AST.NAttribute $ AST.AttribName (AST.NSimple integerTM) highId Nothing)
68 tfvec_index_def = AST.SubtypeIn integerTM (Just tfvec_range)
70 AST.Library $ mkVHDLBasicId "IEEE",
71 mkUseAll ["IEEE", "std_logic_1164"],
72 mkUseAll ["IEEE", "numeric_std"]
75 mkUseAll ["work", "types"]
77 type_package_dec = AST.LUPackageDec $ AST.PackageDec (mkVHDLBasicId "types") ([tfvec_index_decl] ++ vec_decls ++ ty_decls ++ subProgSpecs)
78 type_package_body = AST.LUPackageBody $ AST.PackageBody typesId (concat tyfun_decls)
79 subProgSpecs = concat (map subProgSpec tyfun_decls)
80 subProgSpec = map (\(AST.SubProgBody spec _ _) -> AST.PDISS spec)
81 mktydecl :: (AST.VHDLId, Either AST.TypeDef AST.SubtypeIn) -> AST.PackageDecItem
82 mktydecl (ty_id, Left ty_def) = AST.PDITD $ AST.TypeDec ty_id ty_def
83 mktydecl (ty_id, Right ty_def) = AST.PDISD $ AST.SubtypeDec ty_id ty_def
85 -- Create a use foo.bar.all statement. Takes a list of components in the used
86 -- name. Must contain at least two components
87 mkUseAll :: [String] -> AST.ContextItem
89 AST.Use $ from AST.:.: AST.All
91 base_prefix = (AST.NSimple $ mkVHDLBasicId $ head ss)
92 from = foldl select base_prefix (tail ss)
93 select prefix s = AST.NSelected $ prefix AST.:.: (AST.SSimple $ mkVHDLBasicId s)
96 [(CoreSyn.CoreBndr, CoreSyn.CoreExpr)]
97 -> VHDLState [(AST.VHDLId, [AST.LibraryUnit])]
99 createLibraryUnits binds = do
100 entities <- Monad.mapM createEntity binds
101 archs <- Monad.mapM createArchitecture binds
104 let AST.EntityDec id _ = ent in
105 (id, [AST.LUEntity ent, AST.LUArch arch])
109 -- | Create an entity for a given function
111 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- | The function
112 -> VHDLState AST.EntityDec -- | The resulting entity
114 createEntity (fname, expr) = do
115 -- Strip off lambda's, these will be arguments
116 let (args, letexpr) = CoreSyn.collectBinders expr
117 args' <- Monad.mapM mkMap args
118 -- There must be a let at top level
119 let (CoreSyn.Let binds (CoreSyn.Var res)) = letexpr
121 let vhdl_id = mkVHDLBasicId $ bndrToString fname ++ "_" ++ varToStringUniq fname
122 let ent_decl' = createEntityAST vhdl_id args' res'
123 let AST.EntityDec entity_id _ = ent_decl'
124 let signature = Entity entity_id args' res'
125 modA vsSignatures (Map.insert fname signature)
129 --[(SignalId, SignalInfo)]
131 -> VHDLState VHDLSignalMapElement
132 -- We only need the vsTypes element from the state
135 --info = Maybe.fromMaybe
136 -- (error $ "Signal not found in the name map? This should not happen!")
137 -- (lookup id sigmap)
138 -- Assume the bndr has a valid VHDL id already
139 id = bndrToVHDLId bndr
140 ty = Var.varType bndr
142 if True -- isPortSigUse $ sigUse info
144 type_mark <- vhdl_ty ty
145 return $ Just (id, type_mark)
150 -- | Create the VHDL AST for an entity
152 AST.VHDLId -- | The name of the function
153 -> [VHDLSignalMapElement] -- | The entity's arguments
154 -> VHDLSignalMapElement -- | The entity's result
155 -> AST.EntityDec -- | The entity with the ent_decl filled in as well
157 createEntityAST vhdl_id args res =
158 AST.EntityDec vhdl_id ports
160 -- Create a basic Id, since VHDL doesn't grok filenames with extended Ids.
161 ports = Maybe.catMaybes $
162 map (mkIfaceSigDec AST.In) args
163 ++ [mkIfaceSigDec AST.Out res]
165 -- Add a clk port if we have state
166 clk_port = if True -- hasState hsfunc
168 Just $ AST.IfaceSigDec (mkVHDLExtId "clk") AST.In VHDL.std_logic_ty
172 -- | Create a port declaration
174 AST.Mode -- | The mode for the port (In / Out)
175 -> Maybe (AST.VHDLId, AST.TypeMark) -- | The id and type for the port
176 -> Maybe AST.IfaceSigDec -- | The resulting port declaration
178 mkIfaceSigDec mode (Just (id, ty)) = Just $ AST.IfaceSigDec id mode ty
179 mkIfaceSigDec _ Nothing = Nothing
181 -- | Generate a VHDL entity name for the given hsfunc
183 -- TODO: This doesn't work for functions with multiple signatures!
184 -- Use a Basic Id, since using extended id's for entities throws off
185 -- precision and causes problems when generating filenames.
186 mkVHDLBasicId $ hsFuncName hsfunc
188 -- | Create an architecture for a given function
189 createArchitecture ::
190 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The function
191 -> VHDLState AST.ArchBody -- ^ The architecture for this function
193 createArchitecture (fname, expr) = do
194 signaturemap <- getA vsSignatures
195 let signature = Maybe.fromMaybe
196 (error $ "Generating architecture for function " ++ (pprString fname) ++ "without signature? This should not happen!")
197 (Map.lookup fname signaturemap)
198 let entity_id = ent_id signature
199 -- Strip off lambda's, these will be arguments
200 let (args, letexpr) = CoreSyn.collectBinders expr
201 -- There must be a let at top level
202 let (CoreSyn.Let (CoreSyn.Rec binds) (Var res)) = letexpr
204 -- Create signal declarations for all binders in the let expression, except
205 -- for the output port (that will already have an output port declared in
207 sig_dec_maybes <- mapM (mkSigDec' . fst) (filter ((/=res).fst) binds)
208 let sig_decs = Maybe.catMaybes $ sig_dec_maybes
210 statementss <- Monad.mapM mkConcSm binds
211 let statements = concat statementss
212 return $ AST.ArchBody (mkVHDLBasicId "structural") (AST.NSimple entity_id) (map AST.BDISD sig_decs) (statements ++ procs')
214 procs = map mkStateProcSm [] -- (makeStatePairs flatfunc)
215 procs' = map AST.CSPSm procs
216 -- mkSigDec only uses vsTypes from the state
219 -- | Looks up all pairs of old state, new state signals, together with
220 -- the state id they represent.
221 makeStatePairs :: FlatFunction -> [(StateId, SignalInfo, SignalInfo)]
222 makeStatePairs flatfunc =
223 [(Maybe.fromJust $ oldStateId $ sigUse old_info, old_info, new_info)
224 | old_info <- map snd (flat_sigs flatfunc)
225 , new_info <- map snd (flat_sigs flatfunc)
226 -- old_info must be an old state (and, because of the next equality,
227 -- new_info must be a new state).
228 , Maybe.isJust $ oldStateId $ sigUse old_info
229 -- And the state numbers must match
230 , (oldStateId $ sigUse old_info) == (newStateId $ sigUse new_info)]
232 -- Replace the second tuple element with the corresponding SignalInfo
233 --args_states = map (Arrow.second $ signalInfo sigs) args
234 mkStateProcSm :: (StateId, SignalInfo, SignalInfo) -> AST.ProcSm
235 mkStateProcSm (num, old, new) =
236 AST.ProcSm label [clk] [statement]
238 label = mkVHDLExtId $ "state_" ++ (show num)
239 clk = mkVHDLExtId "clk"
240 rising_edge = AST.NSimple $ mkVHDLBasicId "rising_edge"
241 wform = AST.Wform [AST.WformElem (AST.PrimName $ AST.NSimple $ getSignalId new) Nothing]
242 assign = AST.SigAssign (AST.NSimple $ getSignalId old) wform
243 rising_edge_clk = AST.PrimFCall $ AST.FCall rising_edge [Nothing AST.:=>: (AST.ADName $ AST.NSimple clk)]
244 statement = AST.IfSm rising_edge_clk [assign] [] Nothing
246 mkSigDec :: CoreSyn.CoreBndr -> VHDLState (Maybe AST.SigDec)
248 if True then do --isInternalSigUse use || isStateSigUse use then do
249 type_mark <- vhdl_ty $ Var.varType bndr
250 return $ Just (AST.SigDec (bndrToVHDLId bndr) type_mark Nothing)
254 -- | Creates a VHDL Id from a named SignalInfo. Errors out if the SignalInfo
256 getSignalId :: SignalInfo -> AST.VHDLId
258 mkVHDLExtId $ Maybe.fromMaybe
259 (error $ "Unnamed signal? This should not happen!")
262 -- | Transforms a core binding into a VHDL concurrent statement
264 (CoreSyn.CoreBndr, CoreSyn.CoreExpr) -- ^ The binding to process
265 -> VHDLState [AST.ConcSm] -- ^ The corresponding VHDL component instantiations.
268 -- Ignore Cast expressions, they should not longer have any meaning as long as
269 -- the type works out.
270 mkConcSm (bndr, Cast expr ty) = mkConcSm (bndr, expr)
272 mkConcSm (bndr, app@(CoreSyn.App _ _))= do
273 let (CoreSyn.Var f, args) = CoreSyn.collectArgs app
274 let valargs' = filter isValArg args
275 let valargs = filter (\(CoreSyn.Var bndr) -> not (Id.isDictId bndr)) valargs'
276 case Var.globalIdVarDetails f of
277 IdInfo.DataConWorkId dc ->
278 -- It's a datacon. Create a record from its arguments.
279 -- First, filter out type args. TODO: Is this the best way to do this?
280 -- The types should already have been taken into acocunt when creating
281 -- the signal, so this should probably work...
282 --let valargs = filter isValArg args in
283 if all is_var valargs then do
284 labels <- getFieldLabels (CoreUtils.exprType app)
285 return $ zipWith mkassign labels valargs
287 error $ "VHDL.mkConcSm Not in normal form: One ore more complex arguments: " ++ pprString args
289 mkassign :: AST.VHDLId -> CoreExpr -> AST.ConcSm
290 mkassign label (Var arg) =
291 let sel_name = mkSelectedName bndr label in
292 mkUncondAssign (Right sel_name) (varToVHDLExpr arg)
293 IdInfo.VanillaGlobal -> do
294 -- It's a global value imported from elsewhere. These can be builtin
296 funSignatures <- getA vsNameTable
297 signatures <- getA vsSignatures
298 case (Map.lookup (bndrToString f) funSignatures) of
299 Just (arg_count, builder) ->
300 if length valargs == arg_count then
304 sigs = map (bndrToString.varBndr) valargs
305 sigsNames = map (\signal -> (AST.PrimName (AST.NSimple (mkVHDLExtId signal)))) sigs
306 func = funBuilder sigsNames
307 src_wform = AST.Wform [AST.WformElem func Nothing]
308 dst_name = AST.NSimple (mkVHDLExtId (bndrToString bndr))
309 assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
311 return [AST.CSSASm assign]
314 sigs = map varBndr valargs
315 signature = Maybe.fromMaybe
316 (error $ "Using function '" ++ (bndrToString (head sigs)) ++ "' without signature? This should not happen!")
317 (Map.lookup (head sigs) signatures)
318 arg_names = map (mkVHDLExtId . bndrToString) (tail sigs)
319 dst_name = mkVHDLExtId (bndrToString bndr)
320 genSm = genBuilder 4 signature (arg_names ++ [dst_name])
321 in return [AST.CSGSm genSm]
323 error $ "VHDL.mkConcSm Incorrect number of arguments to builtin function: " ++ pprString f ++ " Args: " ++ pprString valargs
324 Nothing -> error $ "Using function from another module that is not a known builtin: " ++ pprString f
325 IdInfo.NotGlobalId -> do
326 signatures <- getA vsSignatures
327 -- This is a local id, so it should be a function whose definition we
328 -- have and which can be turned into a component instantiation.
330 signature = Maybe.fromMaybe
331 (error $ "Using function '" ++ (bndrToString f) ++ "' without signature? This should not happen!")
332 (Map.lookup f signatures)
333 entity_id = ent_id signature
334 label = "comp_ins_" ++ bndrToString bndr
335 -- Add a clk port if we have state
336 --clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
337 clk_port = Maybe.fromJust $ mkAssocElem (Just $ mkVHDLExtId "clk") "clk"
338 --portmaps = mkAssocElems sigs args res signature ++ (if hasState hsfunc then [clk_port] else [])
339 portmaps = clk_port : mkAssocElems args bndr signature
341 return [AST.CSISm $ AST.CompInsSm (mkVHDLExtId label) (AST.IUEntity (AST.NSimple entity_id)) (AST.PMapAspect portmaps)]
342 details -> error $ "Calling unsupported function " ++ pprString f ++ " with GlobalIdDetails " ++ pprString details
344 -- A single alt case must be a selector. This means thee scrutinee is a simple
345 -- variable, the alternative is a dataalt with a single non-wild binder that
347 mkConcSm (bndr, expr@(Case (Var scrut) b ty [alt])) =
349 (DataAlt dc, bndrs, (Var sel_bndr)) -> do
350 case List.elemIndex sel_bndr bndrs of
352 labels <- getFieldLabels (Id.idType scrut)
353 let label = labels!!i
354 let sel_name = mkSelectedName scrut label
355 let sel_expr = AST.PrimName sel_name
356 return [mkUncondAssign (Left bndr) sel_expr]
357 Nothing -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
359 _ -> error $ "VHDL.mkConcSM Not in normal form: Not a selector case:\n" ++ (pprString expr)
361 -- Multiple case alt are be conditional assignments and have only wild
362 -- binders in the alts and only variables in the case values and a variable
363 -- for a scrutinee. We check the constructor of the second alt, since the
364 -- first is the default case, if there is any.
365 mkConcSm (bndr, (Case (Var scrut) b ty [(_, _, Var false), (con, _, Var true)])) =
367 cond_expr = (varToVHDLExpr scrut) AST.:=: (conToVHDLExpr con)
368 true_expr = (varToVHDLExpr true)
369 false_expr = (varToVHDLExpr false)
371 return [mkCondAssign (Left bndr) cond_expr true_expr false_expr]
372 mkConcSm (_, (Case (Var _) _ _ alts)) = error "VHDL.mkConcSm Not in normal form: Case statement with more than two alternatives"
373 mkConcSm (_, Case _ _ _ _) = error "VHDL.mkConcSm Not in normal form: Case statement has does not have a simple variable as scrutinee"
374 mkConcSm (bndr, expr) = error $ "VHDL.mkConcSM Unsupported binding in let expression: " ++ pprString bndr ++ " = " ++ pprString expr
376 -- Create an unconditional assignment statement
378 Either CoreBndr AST.VHDLName -- ^ The signal to assign to
379 -> AST.Expr -- ^ The expression to assign
380 -> AST.ConcSm -- ^ The resulting concurrent statement
381 mkUncondAssign dst expr = mkAssign dst Nothing expr
383 -- Create a conditional assignment statement
385 Either CoreBndr AST.VHDLName -- ^ The signal to assign to
386 -> AST.Expr -- ^ The condition
387 -> AST.Expr -- ^ The value when true
388 -> AST.Expr -- ^ The value when false
389 -> AST.ConcSm -- ^ The resulting concurrent statement
390 mkCondAssign dst cond true false = mkAssign dst (Just (cond, true)) false
392 -- Create a conditional or unconditional assignment statement
394 Either CoreBndr AST.VHDLName -> -- ^ The signal to assign to
395 Maybe (AST.Expr , AST.Expr) -> -- ^ Optionally, the condition to test for
396 -- and the value to assign when true.
397 AST.Expr -> -- ^ The value to assign when false or no condition
398 AST.ConcSm -- ^ The resulting concurrent statement
400 mkAssign dst cond false_expr =
402 -- I'm not 100% how this assignment AST works, but this gets us what we
404 whenelse = case cond of
405 Just (cond_expr, true_expr) ->
407 true_wform = AST.Wform [AST.WformElem true_expr Nothing]
409 [AST.WhenElse true_wform cond_expr]
411 false_wform = AST.Wform [AST.WformElem false_expr Nothing]
412 dst_name = case dst of
413 Left bndr -> AST.NSimple (bndrToVHDLId bndr)
415 assign = dst_name AST.:<==: (AST.ConWforms whenelse false_wform Nothing)
419 -- Create a record field selector that selects the given label from the record
420 -- stored in the given binder.
421 mkSelectedName :: CoreBndr -> AST.VHDLId -> AST.VHDLName
422 mkSelectedName bndr label =
424 sel_prefix = AST.NSimple $ bndrToVHDLId bndr
425 sel_suffix = AST.SSimple $ label
427 AST.NSelected $ sel_prefix AST.:.: sel_suffix
429 -- Finds the field labels for VHDL type generated for the given Core type,
430 -- which must result in a record type.
431 getFieldLabels :: Type.Type -> VHDLState [AST.VHDLId]
432 getFieldLabels ty = do
433 -- Ensure that the type is generated (but throw away it's VHDLId)
435 -- Get the types map, lookup and unpack the VHDL TypeDef
436 types <- getA vsTypes
437 case Map.lookup (OrdType ty) types of
438 Just (_, Left (AST.TDR (AST.RecordTypeDef elems))) -> return $ map (\(AST.ElementDec id _) -> id) elems
439 _ -> error $ "VHDL.getFieldLabels Type not found or not a record type? This should not happen! Type: " ++ (show ty)
441 -- Turn a variable reference into a AST expression
442 varToVHDLExpr :: Var.Var -> AST.Expr
443 varToVHDLExpr var = AST.PrimName $ AST.NSimple $ bndrToVHDLId var
445 -- Turn a constructor into an AST expression. For dataconstructors, this is
446 -- only the constructor itself, not any arguments it has. Should not be called
447 -- with a DEFAULT constructor.
448 conToVHDLExpr :: CoreSyn.AltCon -> AST.Expr
449 conToVHDLExpr (DataAlt dc) = AST.PrimLit lit
451 tycon = DataCon.dataConTyCon dc
452 tyname = TyCon.tyConName tycon
453 dcname = DataCon.dataConName dc
454 lit = case Name.getOccString tyname of
455 -- TODO: Do something more robust than string matching
456 "Bit" -> case Name.getOccString dcname of "High" -> "'1'"; "Low" -> "'0'"
457 "Bool" -> case Name.getOccString dcname of "True" -> "true"; "False" -> "false"
458 conToVHDLExpr (LitAlt _) = error "VHDL.conToVHDLExpr Literals not support in case alternatives yet"
459 conToVHDLExpr DEFAULT = error "VHDL.conToVHDLExpr DEFAULT alternative should not occur here!"
464 mkConcSm sigs (UncondDef src dst) _ = do
465 src_expr <- vhdl_expr src
466 let src_wform = AST.Wform [AST.WformElem src_expr Nothing]
467 let dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
468 let assign = dst_name AST.:<==: (AST.ConWforms [] src_wform Nothing)
469 return $ AST.CSSASm assign
471 vhdl_expr (Left id) = return $ mkIdExpr sigs id
472 vhdl_expr (Right expr) =
475 return $ (mkIdExpr sigs id) AST.:=: (AST.PrimLit lit)
476 (Literal lit Nothing) ->
477 return $ AST.PrimLit lit
478 (Literal lit (Just ty)) -> do
479 -- Create a cast expression, which is just a function call using the
480 -- type name as the function name.
481 let litexpr = AST.PrimLit lit
483 let ty_name = AST.NSimple ty_id
484 let args = [Nothing AST.:=>: (AST.ADExpr litexpr)]
485 return $ AST.PrimFCall $ AST.FCall ty_name args
487 return $ (mkIdExpr sigs a) AST.:=: (mkIdExpr sigs b)
489 mkConcSm sigs (CondDef cond true false dst) _ =
491 cond_expr = mkIdExpr sigs cond
492 true_expr = mkIdExpr sigs true
493 false_expr = mkIdExpr sigs false
494 false_wform = AST.Wform [AST.WformElem false_expr Nothing]
495 true_wform = AST.Wform [AST.WformElem true_expr Nothing]
496 whenelse = AST.WhenElse true_wform cond_expr
497 dst_name = AST.NSimple (getSignalId $ signalInfo sigs dst)
498 assign = dst_name AST.:<==: (AST.ConWforms [whenelse] false_wform Nothing)
500 return $ AST.CSSASm assign
502 -- | Turn a SignalId into a VHDL Expr
503 mkIdExpr :: [(SignalId, SignalInfo)] -> SignalId -> AST.Expr
505 let src_name = AST.NSimple (getSignalId $ signalInfo sigs id) in
506 AST.PrimName src_name
509 [CoreSyn.CoreExpr] -- | The argument that are applied to function
510 -> CoreSyn.CoreBndr -- | The binder in which to store the result
511 -> Entity -- | The entity to map against.
512 -> [AST.AssocElem] -- | The resulting port maps
514 mkAssocElems args res entity =
515 -- Create the actual AssocElems
516 Maybe.catMaybes $ zipWith mkAssocElem ports sigs
518 -- Turn the ports and signals from a map into a flat list. This works,
519 -- since the maps must have an identical form by definition. TODO: Check
521 arg_ports = ent_args entity
522 res_port = ent_res entity
523 -- Extract the id part from the (id, type) tuple
524 ports = map (Monad.liftM fst) (res_port : arg_ports)
525 -- Translate signal numbers into names
526 sigs = (bndrToString res : map (bndrToString.varBndr) args)
528 -- Turns a Var CoreExpr into the Id inside it. Will of course only work for
529 -- simple Var CoreExprs, not complexer ones.
530 varBndr :: CoreSyn.CoreExpr -> Var.Id
531 varBndr (CoreSyn.Var id) = id
533 -- | Look up a signal in the signal name map
534 lookupSigName :: [(SignalId, SignalInfo)] -> SignalId -> String
535 lookupSigName sigs sig = name
537 info = Maybe.fromMaybe
538 (error $ "Unknown signal " ++ (show sig) ++ " used? This should not happen!")
540 name = Maybe.fromMaybe
541 (error $ "Unnamed signal " ++ (show sig) ++ " used? This should not happen!")
544 -- | Create an VHDL port -> signal association
545 mkAssocElem :: Maybe AST.VHDLId -> String -> Maybe AST.AssocElem
546 mkAssocElem (Just port) signal = Just $ Just port AST.:=>: (AST.ADName (AST.NSimple (mkVHDLExtId signal)))
547 mkAssocElem Nothing _ = Nothing
549 -- | The VHDL Bit type
550 bit_ty :: AST.TypeMark
551 bit_ty = AST.unsafeVHDLBasicId "Bit"
553 -- | The VHDL Boolean type
554 bool_ty :: AST.TypeMark
555 bool_ty = AST.unsafeVHDLBasicId "Boolean"
557 -- | The VHDL std_logic
558 std_logic_ty :: AST.TypeMark
559 std_logic_ty = AST.unsafeVHDLBasicId "std_logic"
561 -- Translate a Haskell type to a VHDL type
562 vhdl_ty :: Type.Type -> VHDLState AST.TypeMark
564 typemap <- getA vsTypes
565 let builtin_ty = do -- See if this is a tycon and lookup its name
566 (tycon, args) <- Type.splitTyConApp_maybe ty
567 let name = Name.getOccString (TyCon.tyConName tycon)
568 Map.lookup name builtin_types
569 -- If not a builtin type, try the custom types
570 let existing_ty = (fmap fst) $ Map.lookup (OrdType ty) typemap
571 case Monoid.getFirst $ Monoid.mconcat (map Monoid.First [builtin_ty, existing_ty]) of
572 -- Found a type, return it
574 -- No type yet, try to construct it
576 newty_maybe <- (construct_vhdl_ty ty)
578 Just (ty_id, ty_def) -> do
579 -- TODO: Check name uniqueness
580 modA vsTypes (Map.insert (OrdType ty) (ty_id, ty_def))
582 Nothing -> error $ "Unsupported Haskell type: " ++ (showSDoc $ ppr ty)
584 -- Construct a new VHDL type for the given Haskell type.
585 construct_vhdl_ty :: Type.Type -> VHDLState (Maybe (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn))
586 construct_vhdl_ty ty = do
587 case Type.splitTyConApp_maybe ty of
588 Just (tycon, args) -> do
589 let name = Name.getOccString (TyCon.tyConName tycon)
592 res <- mk_vector_ty (tfvec_len ty) (tfvec_elem ty)
593 return $ Just $ (Arrow.second Right) res
595 -- res <- mk_vector_ty (sized_word_len ty) ty
596 -- return $ Just $ (Arrow.second Left) res
598 res <- mk_natural_ty 0 (ranged_word_bound ty)
599 return $ Just $ (Arrow.second Right) res
600 -- Create a custom type from this tycon
601 otherwise -> mk_tycon_ty tycon args
602 Nothing -> return $ Nothing
604 -- | Create VHDL type for a custom tycon
605 mk_tycon_ty :: TyCon.TyCon -> [Type.Type] -> VHDLState (Maybe (AST.TypeMark, Either AST.TypeDef AST.SubtypeIn))
606 mk_tycon_ty tycon args =
607 case TyCon.tyConDataCons tycon of
608 -- Not an algebraic type
609 [] -> error $ "Only custom algebraic types are supported: " ++ (showSDoc $ ppr tycon)
611 let arg_tys = DataCon.dataConRepArgTys dc
612 -- TODO: CoreSubst docs say each Subs can be applied only once. Is this a
613 -- violation? Or does it only mean not to apply it again to the same
615 let real_arg_tys = map (CoreSubst.substTy subst) arg_tys
616 elem_tys <- mapM vhdl_ty real_arg_tys
617 let elems = zipWith AST.ElementDec recordlabels elem_tys
618 -- For a single construct datatype, build a record with one field for
620 -- TODO: Add argument type ids to this, to ensure uniqueness
621 -- TODO: Special handling for tuples?
622 let ty_id = mkVHDLExtId $ nameToString (TyCon.tyConName tycon)
623 let ty_def = AST.TDR $ AST.RecordTypeDef elems
624 return $ Just (ty_id, Left ty_def)
625 dcs -> error $ "Only single constructor datatypes supported: " ++ (showSDoc $ ppr tycon)
627 -- Create a subst that instantiates all types passed to the tycon
628 -- TODO: I'm not 100% sure that this is the right way to do this. It seems
629 -- to work so far, though..
630 tyvars = TyCon.tyConTyVars tycon
631 subst = CoreSubst.extendTvSubstList CoreSubst.emptySubst (zip tyvars args)
633 -- | Create a VHDL vector type
635 Int -- ^ The length of the vector
636 -> Type.Type -- ^ The Haskell element type of the Vector
637 -> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created.
639 mk_vector_ty len el_ty = do
640 elem_types_map <- getA vsElemTypes
641 el_ty_tm <- vhdl_ty el_ty
642 let ty_id = mkVHDLExtId $ "vector-"++ (AST.fromVHDLId el_ty_tm) ++ "-0_to_" ++ (show len)
643 let range = AST.ConstraintIndex $ AST.IndexConstraint [AST.ToRange (AST.PrimLit "0") (AST.PrimLit $ show (len - 1))]
644 let existing_elem_ty = (fmap fst) $ Map.lookup (OrdType el_ty) elem_types_map
645 case existing_elem_ty of
647 let ty_def = AST.SubtypeIn t (Just range)
648 return (ty_id, ty_def)
650 let vec_id = mkVHDLExtId $ "vector_" ++ (AST.fromVHDLId el_ty_tm)
651 let vec_def = AST.TDA $ AST.UnconsArrayDef [tfvec_indexTM] el_ty_tm
652 modA vsElemTypes (Map.insert (OrdType el_ty) (vec_id, vec_def))
653 modA vsTypeFuns (Map.insert (OrdType el_ty) (genUnconsVectorFuns el_ty_tm vec_id))
654 let ty_def = AST.SubtypeIn vec_id (Just range)
655 return (ty_id, ty_def)
658 Int -- ^ The minimum bound (> 0)
659 -> Int -- ^ The maximum bound (> minimum bound)
660 -> VHDLState (AST.TypeMark, AST.SubtypeIn) -- The typemark created.
661 mk_natural_ty min_bound max_bound = do
662 let ty_id = mkVHDLExtId $ "nat_" ++ (show min_bound) ++ "_to_" ++ (show max_bound)
663 let range = AST.ConstraintRange $ AST.SubTypeRange (AST.PrimLit $ (show min_bound)) (AST.PrimLit $ (show max_bound))
664 let ty_def = AST.SubtypeIn naturalTM (Just range)
665 return (ty_id, ty_def)
669 ("Bit", std_logic_ty),
670 ("Bool", bool_ty) -- TysWiredIn.boolTy
674 -- Can only contain alphanumerics and underscores. The supplied string must be
675 -- a valid basic id, otherwise an error value is returned. This function is
676 -- not meant to be passed identifiers from a source file, use mkVHDLExtId for
678 mkVHDLBasicId :: String -> AST.VHDLId
680 AST.unsafeVHDLBasicId $ (strip_multiscore . strip_leading . strip_invalid) s
682 -- Strip invalid characters.
683 strip_invalid = filter (`elem` ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ "_.")
684 -- Strip leading numbers and underscores
685 strip_leading = dropWhile (`elem` ['0'..'9'] ++ "_")
686 -- Strip multiple adjacent underscores
687 strip_multiscore = concat . map (\cs ->
693 -- Shortcut for Extended VHDL Id's. These Id's can contain a lot more
694 -- different characters than basic ids, but can never be used to refer to
696 -- Use extended Ids for any values that are taken from the source file.
697 mkVHDLExtId :: String -> AST.VHDLId
699 AST.unsafeVHDLExtId $ strip_invalid s
701 -- Allowed characters, taken from ForSyde's mkVHDLExtId
702 allowed = ['A'..'Z'] ++ ['a'..'z'] ++ ['0'..'9'] ++ " \"#&\\'()*+,./:;<=>_|!$%@?[]^`{}~-"
703 strip_invalid = filter (`elem` allowed)
705 -- Creates a VHDL Id from a binder
710 bndrToVHDLId = mkVHDLExtId . OccName.occNameString . Name.nameOccName . Var.varName
712 -- Extracts the binder name as a String
716 bndrToString = OccName.occNameString . Name.nameOccName . Var.varName
718 -- Get the string version a Var's unique
719 varToStringUniq = show . Var.varUnique
721 -- Extracts the string version of the name
722 nameToString :: Name.Name -> String
723 nameToString = OccName.occNameString . Name.nameOccName
725 recordlabels = map (\c -> mkVHDLBasicId [c]) ['A'..'Z']
727 -- | Map a port specification of a builtin function to a VHDL Signal to put in
729 toVHDLSignalMapElement :: (String, AST.TypeMark) -> VHDLSignalMapElement
730 toVHDLSignalMapElement (name, ty) = Just (mkVHDLBasicId name, ty)